Technical information

8 Porting and Optimizing DSP56800 Applications to DSP56800E 

The optimization techniques applied to the reference code to reach the speed and size improvements are

discussed in the following subsections.

3.1 Delay Slots on Change of Flow

The delayed flow control instructions are designed to increase throughput by eliminating execution cycles

that are wasted when program flow changes. An instruction that affects normal program flow (such as a

branch or jump instruction) requires 2 or 3 additional instruction cycles to flush the execution pipeline. The

program controller stops fetching instructions at the current location and begins to fill the pipeline from the

target address. The execution pipeline stalls while this switch occurs. The additional cycles required to

flush the pipeline are reflected in the total cycle count for each change-of-flow instruction. A special group

of instructions referred to as “delayed” instructions provide a mechanism for executing useful tasks during

these normally wasted cycles.

It is simple to employ these instructions. Replace every BRA, JMP, RTI, and RTS instruction with BRAD,

JMPD, RTID, and RTSD, respectively. These instructions provide a number of delay slots (see Table 6),

which must be filled with instructions.

Table 5. Optimization Gains on the Most Time-Consuming Functions

Function Initial Final Gain

RXBPF 2158 2015 6.63%

RXDEMOD 717 641 10.60%

RXINTP 265 252 4.91%

RXCDAGC 152.67 142.54 6.64%

RXDECIM 118 116 1.69%

tx_fm 192 190 1.04%

RXEQUD 201 199 1.00%

TONEDETECT 318 286 10.06%

RXS1 110.25 106.53 3.37%

RXUSB1 71.74 69.73 2.80%

rx_dscr 125.03 104.47 16.44%

RXEQERR 99.54 95.54 4.02%

tx_scr 81.86 73.33 10.42%

Table 6. Available Delay Slots

Delayed Instructions Number of Delay Slots

BRAD 2

JMPD 2

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