Technical information

6 Porting and Optimizing DSP56800 Applications to DSP56800E 
NOTE:
Throughout this application note, 1 word equals 16 bits.
The size of the data memory does not include the gaps that the circular buffers introduce.
The size of data is the same on both platforms (as expected), but the size of the code is slightly (5 percent)
larger on the ported application. One explanation is that some instructions (such as Bcc) are coded with
more words on the DSP56800E than on the DSP56800. Program space also increases somewhat due to the
different coding of some addressing modes. For example, a MOVE instruction with an immediate operand
and an indexed operand, addressed using R2, is coded on 2 words on the DSP56800E and 1 word on the
DSP56800.
Other interesting information is the processing load of the DSP, measured in million cycles per second
(MCPS). It is computed as the worst-case number of cycles needed to transmit or receive a symbol,
multiplied by 600 symbols per second (V.22 bis assumes that 600 symbols per second are transmitted at
2400 Hz or 1200 Hz), and divided by 1,000,000. Processing load for the full duplex mode includes
processing loads for both transmission and reception. For example, if the worst cases for transmission and
reception are 1352, respectively 9870 cycles, the worst case for full duplex mode is 1352 + 9870 = 11222
cycles. Processing load for full duplex is 11222
× 600 / 1000000 = 6.73 MCPS.
The comparison performed on worst case and processing load illustrates that, as with the speed
measurements for the entire application, the number of cycles on the DSP56800E is slightly more than half
the number of cycles on the DSP56800. See Table 2.
Note that the DSP56800E also runs at higher clock rates; the DSP56800E runs at a clock frequency of
120 MHz, while the DSP56800 runs at 35 MHz. Thus, the actual execution time is much shorter, and the
total improvement in speed obtained by simply porting DSP56800 code to the DSP56800E is significantly
higher.
3 Optimizing the Ported Code
This section summarizes some of the optimization practices that are allowed by the new features of the
improved core architecture. The section also assesses the improvements achieved by implementing these
practices.
The DSP56800E optimization methods that were used do not attempt to make any change in the algorithm
or in the program flow. The modular structure defined by the functions in the reference code is maintained.
The optimization methods were applied at function level, by replacing selected limited code sequences
with optimized equivalents. All of the methods comply with recommended coding practices.
Table 2. Cycle Count Comparison of Ported DSP56800 Code to DSP56800E
Data
Component
or Mode
Worst Case
(Cycles)
Processing Load
(MCPS)
Speedup
Factor
DSP56800 DSP56800E DSP56800 DSP56800E
Transmitter 1352 571 0.81 0.34 2.33
Receiver 9870 5154 5.92 3.09 1.92
Full duplex 11222 5697 6.73 3.43 1.97
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Freescale Semiconductor, Inc.
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