Specifications

8 DSP56800 Hardware Interface Techniques 
System Functions
By default, the pulse shaper functions force internal reset signals to be a minimum of 32 oscillator
clock cycles long. 38T (where T = 1/2 cycle) is required for the DSP56800 core and 1µs is required for
recovery time for the embedded flash. So, 32 works out to be a convenient value (assuming 8MHz
oscillator frequency).
In addition to the reset sources above, two low-voltage detect signals may be used to initiate a
controlled shutdown of the chip when the supply drops below acceptable levels. These low-voltage
detect circuits are set up as high-priority interrupts. They can be masked if desired. See Chapter 16 in
the DSP56F80x User’s Manual.
Logic is provided on the DSP56800 to generate a clean power-on RESET signal. An example RESET
circuit is shown in Figure 9.
Figure 9. Schematic Diagram of the RESET Interface
2.4.2 External Interrupt Pin Interface
Figure 10 shows an example hardware interface to the external interrupt pins IRQA and IRQB.
Figure 10. Schematic Diagram of the External Interrupt Pin Interface
RESET
PUSHBUTTON
MANUAL RESET
P_RESET
RESET
+3.3V
DSP56F807
IRQA
IRQB
+3.3V
+3.3V
10K
10K
SW2
SW3
0.1µF
0.1µF
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
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