Specifications

System Functions
 DSP56800 Hardware Interface Techniques 5
where C depends on die area and output capacitive loading as described below, V
DD
is the digital
supply voltage, and f is the operating frequency of the device. This results from a total capacitance C
being charged every T seconds, where T is the machine cycle time. The charge required from the
power supply for each cycle T is Q = C * V
DD
. Hence Idigital = Q/T = C * V
DD
* f. Further, Idigital
varies with temperature as described in subsequent sections.
I
analog
depends on output loading and other factors as described below.
2.3.2 Mode of Operation
The DSP56800 devices support two low-power modes, referred to as STOP and WAIT modes. These
are described in detail in the associated device User Manuals, and the resulting reductions in supply
current requirement are given in the device Electrical Specifications. Both modes put the CPU to sleep.
The PLL and peripheral bus continue to run in WAIT mode, but not in STOP mode. The ADC is
placed in a low-power mode in both cases.
2.3.3 Variation with Respect to Supply Voltage
The digital supply current requirement of CMOS devices with respect to supply voltage is
approximately linear, as shown in Figure 5. below for the DSP56805. The DSP56800 devices possess
both a CMOS current requirement and an analog current requirement. The variation of analog supply
current with respect to analog supply voltage is shown in Figure 6. These curves are consistent with
the model described in Section 2.3.1.
Figure 5. Total IDD vs. VDD
Total IDD vs VDD (nom Temp, 80 MHz PLL)
72
74
76
78
80
82
84
86
88
90
92
VDD min VDD nom VDD max
VDD
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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