Specifications

System Functions
 DSP56800 Hardware Interface Techniques 3
9. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V
DD
and GND circuits.
10. All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
11. Take special care to minimize noise levels on the V
REF
, VDDA and VSSA pins.
2.2 Providing Clock to the DSP56800
The DSP56F80x system clock can be derived from a crystal or an external system clock signal. To
generate a reference frequency using the internal oscillator, a reference crystal must be connected
between the EXTAL and XTAL pins. For the DSP56801 (only), an additional clock option is
available, which is the use of an internal relaxation oscillator which requires no external circuitry
whatsoever.
2.2.1 Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 1. In Figure 2, a typical crystal oscillator
circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal, because
crystal parameters determine the component values required to provide maximum stability and reliable
start-up. The load capacitance values used in the oscillator circuit design should include all stray layout
capacitances. The crystal and associated components should be mounted as closely as possible to the
EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Table 1: PLL Timing
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C
Figure 2. Crystal Oscillator
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL
1
1
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8 MHz input crystal.
f
osc
488MHz
PLL output frequency f
op
40 —80MHz
PLL stabilization time
2
2
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
t
plls
—110ms
Sample External Crystal Parameters:
R
z
= 10 MΩ
Crystal Frequency = 4–8 MHz (optimized for 8 MHz)
EXTAL XTAL
R
z
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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