Specifications

2 DSP56800 Hardware Interface Techniques
System Functions
Figure 1. Schematic Diagram of the Power Supply
The DSP56800 devices include both analog and digital circuitry, making noise control a high priority.
Several design recommendations relating to power, ground and PCB design are given below.
1. All V
DD
supply pins must be bypassed with a 0.01-0.1µF bypass capacitor (see recommendation
(5) below). The general rule in selecting the capacitor value is to choose the highest value
available in the designer’s selection of capacitor package, although there are more sophisticated
techniques in capacitor-value selection (see Reference 1. in Section 6). The more sophisticated
rules, however, require rather extensive (and typically unavailable) knowledge of output loading
and various characteristics of the user's PCB. The simpler rule follows from the objective of
minimizing capacitor lead inductance by minimizing package size, while ensuring that adequate
electrical charge will be directly available to the processor on a clock-by-clock basis.
Surface-mount capacitors are highly recommended, as these devices have very low-inductance
connections. Inductance of capacitor leads can cause ground bounce, EMI, and signal crosstalk
and degradation.
2. The overall system itself must be bypassed at the power entry point to the PCB with a sufficiently
large capacitor to counteract the inductance of the power supply leads and to be able to deliver
sufficient charge to all bypass capacitors each clock cycle. Recommended is a 100µF tantalum
capacitor.
3. The PCB should be divided into separate sections for analog and digital functions. Ultimately the
analog and digital grounds should be connected at a single -point ground. Additionally, power and
ground planes should be employed in the user’s PCB, minimizing return-path inductance and
isolating digital switching noise from analog circuitry.
4. Provide a low-impedance path from the board power supply to each V
DD
pin on the DSP, and
from the board ground to each V
SS
(GND) pin.
5. The minimum bypass requirement is to place 0.01–0.1µF capacitors positioned as closely as
possible to the package supply pins. The recommended bypass configuration is to place one
bypass capacitor on each of the V
DD
/V
SS
pairs, including V
DDA
/V
DDSA.
6. Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
DD
and
V
SS
(GND) pins are less than 0.5” per capacitor lead.
7. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V
DD
and GND.
8. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
+12V DC
+5.0V
Regulator
POWER ON
GREEN LED
+3.3V
Regulator
+3.3V Digital
+3.3V Analog
+5.0V
+3.3V
DSP56F80x
Other System
Parts
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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