Specifications

16 DSP56800 Hardware Interface Techniques 
Memory Interfaces
3.2.3.1 Memory Paging Using GPIO
Figure 14 below shows a simple technique to select different banks of memory. A given bank of
memory is enabled by setting the appropriate GPIO pin to zero. Note that only one bank of memory
can be enabled at any given time. Therefore, the programmer must manage the GPIO pins carefully,
allowing only one pin to be set low in the expanded memory system. Pseudocode for using this
technique is given as follows.
Initialize GPIO pin control registers
For a page transition (indicated by software monitoring or by an interrupt handler):
i) Jump to internal program memory
ii) Modify GPIO control registers as appropriate
iii) Jump to the new external page
Figure 14. Expansion Memory Example Using GPIO
3.2.3.2 Memory Paging Using Latched Data as Address
Figure 15 shows a second way to page external memory. This technique multiplies the address space to
8 times 64K words = 512K words of both program and data space. Each memory bank is selected by
an output from the ‘138 decoder. The decoder’s inputs are driven from 3 outputs of a 4-bit latch, fed by
3 data lines from the DSP56800 device. A dedicated GPIO pin controls the clock to the latch. When
the GPIO pin is set high, the latch cannot be written. To execute a page transition, the GPIO pin must
be set low via software control, followed by an external data write to the latch. The page must then be
locked in in software by setting the GPIO pin back to one. Further, the GPIO pin can be used in
conjuction with other logic to disable writing of any other external devices during a page transition.
The following summarizes the steps required in software to use this technique.
DSP56F807
GS72116
A0-A15
PS
D0-D15
RD
WR
A1-A16
A0
DQ0-DQ15
OE
WE
CE
+3.3V
2.5K
GPIOB
n
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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