Specifications

Memory Interfaces
 DSP56800 Hardware Interface Techniques 15
Then:
Top = 1/50e6 = 20ns
WS = 0
t
ACC
= Top*0 + (Top – 11.5) = 8.5ns
Many SRAM devices are available in this speed range.
3.2.2 Program and Data Memory Example Interface
The DSP56807 EVM uses one bank of 128K×16-bit Fast Static RAM (GSI GS72116, labelled U2) for
external memory expansion; see the FSRAM schematic diagram in Figure 13. This physical memory
bank is split into two logical memory banks of 64Kx16-bits: one for program memory and the other for
data memory. By using the DSP’s program strobe, PS
, signal line along with the memory chip’s A0
signal line, half of the memory chip is selected when program memory accesses are requested and the
other half of the memory chip is selected when data memory access are requested. This memory bank
will operate with zero wait state accesses while the DSP56F807 is running at 70MHz. However, when
running at 80MHz, the memory bank operates with four wait state accesses.
Figure 13. Schematic Diagram of the External Memory Interface
3.2.3 Memory Expansion Techniques
The total memory space addressable by the DSP56800 device is 64K words for program memory, plus
64K words for data memory. However, paging techniques can be implemented in hardware as shown
in the following two examples. The application developer must take appropriate steps in software
development to accommodate page boundary transitions.
DSP56F807
GS72116
A0-A15
PS
D0-D15
RD
WR
A1-A16
A0
DQ0-DQ15
OE
WE
CE
+3.3V
JG1
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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