Specifications

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14 DSP56800 Hardware Interface Techniques 

Memory Interfaces

3.1.7 Normal Expanded Mode (Mode 2)

In the Normal Expanded mode (Mode 2), all 32,768 words of internal program ROM are enabled for

reads and fetches. Writes to the lower 128 words of internal program space will write to the internal

program RAM. The reset vector location in Mode 2 is at P:$E000 in the external program RAM

(P:$E002 for COP timer reset).

Mode 2 is identical to Mode 0 except that the reset vectors are in external memory. This feature

provides additional flexibility for application development.

3.1.8 Development Mode (Mode 3)

Mode 3 is the Development mode, in which the entire 65,536 words of program memory space is

external. No internal program memory space can be accessed. The reset vector location in Mode 3 is at

P:$0000 in the external program memory space (P:$0002 for COP timer reset). Mode 3 is the primary

mode for application development on the DSP56824.

3.2 External Memory Interfaces

The DSP56800 family devices (excluding the DSP56801) have an external 16-bit multiplexed data bus

that can be used for program word or data accesses to memory devices, including ROM, FLASH,

EEPROM, or SRAM. The PS

and DS outputs from the DSP device differentiate the two types of

accesses. External bus accesses are referred to as asynchronous, as the timing specifications given in

the appropriate Electrical Specifications for each device are not made with respect to the DSP clock.

3.2.1 Wait State Management for the DSP56800

Optimization of external memory use, particularly for DSP56800 devices, depends on several factors

that can be taken into consideration for a given hardware design.

First, as much internal memory as possible for a given application should be used, as all internal

accesses require zero wait states.

Second, if external memory must be used, partitioning the total code into two pieces can be beneficial.

These two pieces are i) often used and repeated code, and ii) code used or needed less frequently.

Third, wait states (WS) are programmable for the values 0, 4, 8 and 12. Wait states have traditionally

provided a means for accessing slower memories motivated either by technology limitations or to the

cost advantage offered by slower memory devices. Each wait state extends external bus accesses by

2*WS clock periods. Note that wait state values are independently programmable for external X (data)

memory and external program memory. For example, the clock period (Top) for a device running at

80MHz (CPU clock of 40MHz) is 12.5ns. External memory access time is given by :

ACC

= Top*WS + (Top-11.5) (ns)

For example, 4 wait states for a CPU running at 40MHz (clock rate of 80MHz) results in a memory

access time of 12.5*4 + (12.5-11.5) = 51ns.

Many modern memory devices, such as SRAMs, cannot operate with 0 wait states but can, however,

be accessed in the sub-10ns range. Therefore, for certain applications, it is worthwhile to consider

selecting a lower clock frequency in order to be able to access external memory with no wait states.

This is particularly true of applications that must make heavy use of external memory and is

exemplified by the following:

Suppose an application requires only 25MIPS, rather than the maximum of 40MIPS.

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cale Semiconductor,

Freescale Semiconductor, Inc.

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