Specifications

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Memory Interfaces

 DSP56800 Hardware Interface Techniques 13

The MODA and MODB pins are sampled as the DSP56824 leaves the Reset state, and the initial

operating mode of the chip is set accordingly. After the Reset state is exited, the MODA and MODB

pins become interrupt pins, IRQA

and IRQB. One of four initial operating modes is selected, based on

the values detected on MODA and MODB:

• Single Chip mode (Mode 0 or Mode 1)

• Normal Expanded mode (Mode 2)

• Development mode (Mode 3)

Chip operating modes can also be changed by writing to the MB and MA bits in the OMR. Changing

operating modes does not reset the DSP56824. To prevent an interrupt from going to the wrong

memory location, interrupts should be disabled immediately before changing the OMR. Also, one

no-operation (NOP) instruction should be included after changing the OMR to allow for remapping to

occur.

Note: On a Computer Operating Properly (COP) reset, the MA and MB bits (in the OMR) revert to

the values originally latched from the MODA and MODB pins on deassertion of RESET

These values determine the COP reset vector. For example, if the DSP56xxx left hardware

reset in Mode 2 and the mode bits in the OMR were later changed to specify Mode 3, a COP

reset would use reset vector P:$E002 (for Mode 2) for its reset vector, and not P:$0002 (for

Mode 3).

3.1.5 Single Chip Bootstrap Mode (Mode 0)

Mode 0 is the Single Chip bootstrap mode in which all the internal program and data memory space is

enabled; see Table 3. Mode 0 can be entered by either pulling the MODA and MODB pins low before

resetting the chip or by writing to the OMR and clearing the MA and MB bits. Writes to the lower 128

words of internal program space will write to the internal program RAM. The reset vector location in

Mode 0 is P:$0000 in the internal program ROM (P:$0002 for COP timer reset).

Mode 0 is useful when exiting the Reset state for applications that execute primarily from internal

program ROM. Write access to the internal program RAM allows an application to copy interrupt

vectors and program code from program ROM to identically addressed locations in program RAM

without changing operating modes.

3.1.6 Single Chip User (Mode 1)

Mode 1 is the Single Chip user mode in which 34,640 (32,768 – 128) words of internal program ROM

are enabled for reads and fetches. All accesses to the lower 128 words of internal program space are to

the internal program RAM. The reset vector location in Mode 1 is P:$7F80 in the internal program

ROM (P:$7F82 for COP timer reset). The user should observe that these reset vectors are located in the

area reserved for the bootstrap program.

Mode 1 is the ordinary user mode for applications that execute primarily from internal program ROM

or for applications that must access the internal program RAM. The internal program RAM is typically

loaded in Mode 0 or by the bootstrap program in Mode 1. For more information on loading the internal

program RAM in this manner, see Appendix A, “Bootstrap Program”, in the DSP56824 User’s

Manual.

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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