Specifications

Memory Interfaces

 DSP56800 Hardware Interface Techniques 11

This section includes aspects of the JTAG implementation specific to the DSP56F801 through 807.

This data is intended to be utilized with IEEE 1149.1a. The discussion includes those items required

by the standard to be defined and, in certain cases, provides additional information specific to the

DSP56F801/803/805/807. For internal details and applications of the standard, refer to IEEE 1149.1a.

3. Memory Interfaces

Memory configuration is controlled slightly differently for the DSP56800 and DSP5682x devices as

described below. From a hardware perspective, the DSP56800 device memory map is controlled by a

single pin (EXTBOOT), while for DSP5682x devices, the MODA and MODB pins control the

memory configuration.

3.1 DSP56F800 Memory Configuration

The DSP56800 chips have two valid operating modes determining the memory maps for program

memory. Operating modes can be selected either by applying the appropriate signal to the EXTBOOT

pin during reset, or by writing to the Operating Mode Register (OMR) and changing the MA and MB

bits.

The EXTBOOT pin is sampled as the chip leaves the reset state, and the initial operating mode of the

chip is set accordingly.

Chip operating modes can also be changed by writing to the operating mode bits MB and MA in the

OMR. Changing operating modes does not reset the chip. Interrupts should be disabled immediately

before changing the OMR. This will prevent an interrupt from going to the wrong memory location.

Also, one No-Operation (NOP) instruction should be included after changing the OMR to allow for

re-mapping to occur.

Note: Upon Computer Operating Properly (COP) reset, the MA and MB bits will revert to the values

originally latched from the EXTBOOT pin in contradiction of RESET

, hardware reset. These

original mode values determine the COP reset vector.

3.1.1 Single Chip Mode: Start-up (Mode 0)

Mode zero is the single-chip mode. Internal Program RAM (PRAM) and PFLASH are enabled for

reads and fetches. The DSP56xxx have two sub-modes for:

1. Mode 0A, boot mode, where all memory is internal

2. Mode 0B, non-boot mode, where the first 32K of memory is internal and the second 32K is

external

Table 2: DSP56800 Program Memory Chip Operating Modes

State of EXTBOOT upon reset MB MA Chip operating mode

0 0 0 Mode 0

NORMAL Operation

N/A 0 1 NOT SUPPORTED

N/A 1 0

1 1 1 Mode 3

EXTERNAL ROM

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cale Semiconductor,

Freescale Semiconductor, Inc.

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