Specifications
10 DSP56800 Hardware Interface Techniques
System Functions
This section is dedicated to testing and debugging retention, but specifically through the Joint Test
Action Group, (JTAG) and the OnCE module.
DSP56F801/803/805/807 provides board and chip-level testing capability through two on-chip
modules, both accessed through the JTAG port/OnCE module interface:
• On-chip Emulation (OnCE) module
• Test Access Port (TAP) and 16-state controller, also known as the Joint Test Action Group
(JTAG) port
Presence of the JTAG port/OnCE module interface permits insertion of the DSP chip into a target
system while retaining debug control. This capability is especially important for devices without an
external bus, because it eliminates the need for a costly cable to bring out the footprint of the chip
required by a traditional emulator system.
The OnCE module is a Freescale-designed module used in Digital Signal Processor (DSP) chips to
debug application software employed with the chip. The port is a separate on-chip block allowing
non-intrusive DSP interaction with accessibility through the pins of the JTAG interface. The OnCE
module makes it possible to examine registers, memory, or on-chip peripherals’ contents in a special
debug environment. This avoids sacrificing any user-accessible on-chip resources to perform
debugging. See Chapter 17, OnCE Module, in the DSP56F80x User’s Manual for details on the
OnCE module implementation of the DSP56F801,803, 805 and 807 series.
The JTAG port is a dedicated user-accessible TAP compatible with the IEEE 1149.1a-1993 Standard
Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density
circuit boards have led to the development of this proposed standard under the sponsorship of the Test
Technology Committee of IEEE and the JTAG. DSP56F 801 through 807 supports circuit board test
strategies based on this standard.
Five dedicated pins interface to the TAP containing a 16-state controller. The TAP uses a boundary
scan technique to test the interconnections between integrated circuits after they are assembled onto a
Printed Circuit Board (PCB). Boundary scans allow a tester to observe and control signal levels at
each component pin through a shift register placed next to each pin. This is important for testing
continuity and determining if pins are stuck at a one or zero level.
Features of the TAP port include the following:
• Perform boundary scan operations to test circuit board electrical continuity
• Bypass the DSP for a given circuit board test by replacing the Boundary Scan Register (BSR)
with a single-bit register
• Sample the DSP system pins during operation and transparently shift out the result in the CSR;
pre-load values to output pins prior to invoking the EXTEST instruction
• Disable the output drive to pins during circuit board testing
• Provide a means of accessing the OnCE module controller and circuits to control a target
system
• Query identification information, manufacturer, pat number, and version from a DSP chip
• Force test data onto the outputs of a DSP IC while replacing its BSR in the serial data path
with a single bit register
• Enable a weak pull-up current device on all input signals of a DSP IC, helping to assure
deterministic test results in the presence of continuity fault during interconnect testing
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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