Specifications

ManualsBrandsMotorola ManualsComputer equipmentDSP56800

DSP56800 Hardware

Interface

Technique

Freescale

Semiconductor Application Note

Order by AN1920/D

Freescale Order Number

Rev. 0, 06/2001

DSP56800 Hardware

Interface Techniques

David Zalac

1. Introduction

Interface techniques to the DSP56800 Embedded DSP

Controller family of devices are shown. This includes system

interface, memory interface and peripheral interface

examples. This document is intended to cover device

interfacing for the DSP56F801, DSP56F803, DSP56F805,

DSP56F807 and DSP56824 products.

2. System Functions

In this section, we examine the essential requirements to

power and clock the DSP56800, and address other system

functions including power management, hardware interrupts,

and the processors’ JTAG/OnCE port.

2.1 Providing Supply Voltage to the

DSP56800

The DSP56800 specification for supply voltage is 3.0V

(minimum) to 3.6V (maximum).

This voltage source is to be applied to the all of the device’s

pins. Internally, this voltage is regulated down to 2.5V

for the core digital circuitry. The analog supply and reference

voltages V

DDA

and V

REF

should satisfy the constraints

REF

<= V

DDA

<= V

The processor supply current is application-dependent and

can be computed using the data supplied in the device’s

Electrical Specification.

An example power supply circuit is given in Figure 1.

Contents

1. Introduction ....................................1

2. System Functions ...........................1

2.1 Providing Supply Voltage to the

DSP56800........................................1

2.2 Providing Clock to the DSP56800..3

2.3 Power Management.........................4

2.4 Reset/Interrupt Interfaces................7

2.5 JTAG/OnCE Interface.....................9

3. Memory Interfaces .......................11

3.1 DSP56F800 Memory

Configuration.................................11

3.2 External Memory Interfaces..........14

4. Peripheral Interfaces ....................18

4.1 GPIO Interface Example...............18

4.2 CAN Interface (DSP56F805)........18

4.3 Codec Interface (DSP56824) ........19

4.4 PWM Interface..............................21

4.5 Motor Protection Logic.................22

4.6 SCI Interface .................................24

4.7 Quadrature Decoder Interface.......25

4.8 Zero-Crossing Detection...............25

5. Conclusion ................................... 25

6. References ....................................26

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Summary of content (28 pages)

PAGE 1
Freescale Semiconductor, Inc. Freescale Order by AN1920/D Freescale Order Number Rev. 0, 06/2001 Contents DSP56800 Hardware Interface Techniques 1. Introduction ....................................1 David Zalac 2. System Functions ...........................1 1. Introduction Interface techniques to the DSP56800 Embedded DSP Controller family of devices are shown. This includes system interface, memory interface and peripheral interface examples.
PAGE 2
Freescale Semiconductor, Inc. System Functions +3.3V +5.0V +12V DC +3.3V Regulator +5.0V Regulator +3.3V Digital +3.3V Analog DSP56F80x POWER ON Other System Parts Freescale Semiconductor, Inc... GREEN LED Figure 1. Schematic Diagram of the Power Supply The DSP56800 devices include both analog and digital circuitry, making noise control a high priority. Several design recommendations relating to power, ground and PCB design are given below. 1. All VDD supply pins must be bypassed with a 0.01-0.
PAGE 3
Freescale Semiconductor, Inc. System Functions 9. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. 10. All inputs must be terminated (i.e., not allowed to float) using CMOS levels. 11. Take special care to minimize noise levels on the V REF, VDDA and VSSA pins. 2.
PAGE 4
Freescale Semiconductor, Inc. System Functions 2.2.2 External Clock Source The recommended method of connecting an external clock is given in Figure 3. The external clock source is connected to XTAL and the EXTAL pin is grounded. DSP56F805 XTAL EXTAL External Clock GND Freescale Semiconductor, Inc... Figure 3. Connecting an External Clock Signal using XTAL It is possible to instead drive EXTAL with an external clock, though this is not the recommended method.
PAGE 5
Freescale Semiconductor, Inc. System Functions where C depends on die area and output capacitive loading as described below, VDD is the digital supply voltage, and f is the operating frequency of the device. This results from a total capacitance C being charged every T seconds, where T is the machine cycle time. The charge required from the power supply for each cycle T is Q = C * VDD. Hence Idigital = Q/T = C * VDD * f. Further, Idigital varies with temperature as described in subsequent sections.
PAGE 6
Freescale Semiconductor, Inc. System Functions IDDA vs. VDDA (nom Temp, 80 MHz PLL) 55.5 55 54.5 54 Freescale Semiconductor, Inc... 53.5 53 52.5 52 VDDA min VDDA nom VDDA max VDDA Figure 6. IDDA vs. VDDA 2.3.4 Variation with Respect to Operating Frequency The digital supply current requirement of CMOS devices with respect to frequency is approximately linear, as shown in Figure 7 below. These curves are consistent with the device current model. IDD vs.
PAGE 7
Freescale Semiconductor, Inc. System Functions 2.3.5 Variation with Respect to Output Loading Output loading influences supply current requirement in a manner similar to that described by the model given in Section 2.3.1. Output load current for a given output pin is the sum of DC and AC currents. The DC current requirement is that imposed by connected devices, such as TTL inputs.
PAGE 8
Freescale Semiconductor, Inc. System Functions By default, the pulse shaper functions force internal reset signals to be a minimum of 32 oscillator clock cycles long. 38T (where T = 1/2 cycle) is required for the DSP56800 core and 1µs is required for recovery time for the embedded flash. So, 32 works out to be a convenient value (assuming 8MHz oscillator frequency).
PAGE 9
Freescale Semiconductor, Inc. System Functions 2.4.3 GPIO Pin Configured as Interrupt Interface An example interface to GPIO pins found on the DSP56800 device is shown in Figure 11. These inputs can be configured as interrupt sources or as general-purpose I/O’s as described further in the device User’s Manuals. +3.3V DSP56F807 10K GP #1 SWITCH PD3 Freescale Semiconductor, Inc... +3.3V GP #2 SWITCH 10K PD4 +3.3V START/STOP SWITCH 10K PD5 Figure 11. Run/Stop and General Purpose Switches 2.
PAGE 10
Freescale Semiconductor, Inc. System Functions This section is dedicated to testing and debugging retention, but specifically through the Joint Test Action Group, (JTAG) and the OnCE module.
PAGE 11
Freescale Semiconductor, Inc. Memory Interfaces This section includes aspects of the JTAG implementation specific to the DSP56F801 through 807. This data is intended to be utilized with IEEE 1149.1a. The discussion includes those items required by the standard to be defined and, in certain cases, provides additional information specific to the DSP56F801/803/805/807. For internal details and applications of the standard, refer to IEEE 1149.1a. 3. Memory Interfaces Freescale Semiconductor, Inc...
PAGE 12
Freescale Semiconductor, Inc. Memory Interfaces If EXTBOOT is asserted low during reset, then Mode 0A: boot is automatically entered when exiting Reset mode. For DSP56F801, Mode0B is not supported because there is no external memory interface. Note: Locations zero through three in the program memory space are actually mapped to the first four locations in the Boot Flash. Mode zero is useful to enter when coming out of reset for applications while executing primarily from internal program memory.
PAGE 13
Freescale Semiconductor, Inc. Memory Interfaces The MODA and MODB pins are sampled as the DSP56824 leaves the Reset state, and the initial operating mode of the chip is set accordingly. After the Reset state is exited, the MODA and MODB pins become interrupt pins, IRQA and IRQB. One of four initial operating modes is selected, based on the values detected on MODA and MODB: • Single Chip mode (Mode 0 or Mode 1) • Normal Expanded mode (Mode 2) • Development mode (Mode 3) Freescale Semiconductor, Inc...
PAGE 14
Freescale Semiconductor, Inc. Memory Interfaces 3.1.7 Normal Expanded Mode (Mode 2) In the Normal Expanded mode (Mode 2), all 32,768 words of internal program ROM are enabled for reads and fetches. Writes to the lower 128 words of internal program space will write to the internal program RAM. The reset vector location in Mode 2 is at P:$E000 in the external program RAM (P:$E002 for COP timer reset). Mode 2 is identical to Mode 0 except that the reset vectors are in external memory.
PAGE 15
Freescale Semiconductor, Inc. Memory Interfaces Then: Top = 1/50e6 = 20ns WS = 0 tACC = Top*0 + (Top – 11.5) = 8.5ns Many SRAM devices are available in this speed range. Freescale Semiconductor, Inc... 3.2.2 Program and Data Memory Example Interface The DSP56807 EVM uses one bank of 128K×16-bit Fast Static RAM (GSI GS72116, labelled U2) for external memory expansion; see the FSRAM schematic diagram in Figure 13.
PAGE 16
Freescale Semiconductor, Inc. Memory Interfaces 3.2.3.1 Memory Paging Using GPIO Figure 14 below shows a simple technique to select different banks of memory. A given bank of memory is enabled by setting the appropriate GPIO pin to zero. Note that only one bank of memory can be enabled at any given time. Therefore, the programmer must manage the GPIO pins carefully, allowing only one pin to be set low in the expanded memory system. Pseudocode for using this technique is given as follows.
PAGE 17
Freescale Semiconductor, Inc. Memory Interfaces Initialize GPIO control registers For a page transition: i) Set GPIO to zero ii) Execute external write cycle to latch with 12 waitstates iii) Set GPIO to one Note that one address of each bank must be reserved, as the write cycle to the latch will also write the corresponding address in the previously selected bank. DSP56F807 Freescale Semiconductor, Inc...
PAGE 18
Freescale Semiconductor, Inc. Peripheral Interfaces 4. Peripheral Interfaces The following sections provide example interfaces to DSP56800 peripherals. The interfaces have been implemented and tested on Evaluation Module (EVM) hardware using various members of the DSP56800 family. 4.1 GPIO Interface Example An example interface making use of the DSP56800 GPIO pins is given below. The GPIO pins are controllable via SDK driver routines. Refer to the SDK Programmer’s Guide for details.
PAGE 19
Freescale Semiconductor, Inc. Peripheral Interfaces CAN CONNECTOR J1 1 3 5 7 X DSP56F805 +5.0V X X U20 MSCAN_TX 1 MSCAN_RX 4 8 2 4 6 8 X X X X 3 VCC 5 VREF TXD RXD CANH CANL SLOPE GND 7 6 1 2 120 2 PCA82C250T Freescale Semiconductor, Inc... CAN TERMINATION X X X J2 1 3 5 7 2 4 6 8 X X X X DAISY-CHAIN CAN CONNECTOR Figure 17.
PAGE 20
Freescale Semiconductor, Inc. Peripheral Interfaces CODEC Enable (SSI Port Connector) DSP56824 MC145483 J1 STD DR SRD DT STCK BCLKR, BCLKT, MCLK FST, FSR STFS SRCK Freescale Semiconductor, Inc... SRFS Figure 18.
PAGE 21
Freescale Semiconductor, Inc. Peripheral Interfaces DSP56F807 MAX5251 MOSI J1 DIN MISO DOUT SCLK SCLK OUT A OUT B OUT C OUT D PB4 CS RSTO CL D/A CONNECTOR D/A 0 D/A 1 D/A 2 D/A 3 1 2 3 4 5 6 7 8 Vref R1 +3.3VA Freescale Semiconductor, Inc... 10K Figure 19. Serial 10-bit, 4-Channel D/A Converter 4.4 PWM Interface The sections below describe example interfaces to the PWM module(s) available on DSP56800 devices. The DSP56F807 has two independent groups of dedicated PWM units.
PAGE 22
Freescale Semiconductor, Inc. Peripheral Interfaces 4.5 Motor Protection Logic The DSP56F807EVM contains two UNI-3 connectors that interface with various motor drive boards, Primary UNI-3 and Secondary UNI-3. The DSP can sense error conditions generated by the motor power stage boards via signals on the UNI-3 connector. The motor driver board’s Motor Supply DC Bus Voltage, Current and Motor Phase Currents are sensed on a separate power stage board.
PAGE 23
Freescale Semiconductor, Inc. Peripheral Interfaces Table 6: FAULTA1 Source Selection Jumper JG1 Comment 1–2 Phase A Over-Current Sense input 2–3 DC Bus Over-Current Sense input DC BUS VOLTAGE SENSE V_sense_DCB Freescale Semiconductor, Inc... +3.3V +5.0V +5.0V + FAULT0 – LM393 EXAMPLE DC PHASE CURRENT SENSE +5.0V +3.3V +5.0V + FAULT2 PHB_IS – LM393 Figure 22.
PAGE 24
Freescale Semiconductor, Inc. Peripheral Interfaces 4.6 SCI Interface An example of an SCI interface is that provided by the DSP56F807EVM. The EVM provides an RS-232 interface by the use of an RS-232 level converter, (Maxim MAX3245EEAI). Refer to the RS-232 schematic diagram in Figure 23. The RS-232 level converter transitions the SCI UART’s 3.3V signal levels to RS-232 compatible signal levels and connects to the host’s serial port via connector P3.
PAGE 25
Freescale Semiconductor, Inc. Conclusion 4.7 Quadrature Decoder Interface The DSP56F807EVM board contains a Primary and Secondary Quadrature Encoder/Hall-Effect interface connected to the DSP’s first and second Quad Encoder input ports. The circuit is designed to accept +3.0V to +5.0V encoder or Hall-Effect sensor inputs. Input noise filtering is supplied on the input path for the Quadrature Encoder/Hall-Effect interface, along with additional noise rejection circuitry inside the DSP.
PAGE 26
Freescale Semiconductor, Inc. References 6. References 1. Howard W. Johnson and Martin Graham, “High-Speed Digital Design”, PTR Prentice-Hall, 1993 2. DSP5680x User’s Manual, DSP56F801-7UM/D 3. DSP56824 User’s Manual, DSP56824UM/D 4. DSP56800 Family Manual, DSP56800FM/D 5. DSP56F803 Evaluation Module Hardware User’s Manual, DSP56F803 6. DSP56F805 Evaluation Module Hardware User’s Manual, DSP56F05EVMUM/D 7. DSP56F807 Evaluation Module Hardware User’s Manual, DSP56F807EVMUM/D Freescale Semiconductor, Inc.
PAGE 27
Freescale Semiconductor, Inc.
PAGE 28
Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com Freescale Semiconductor, Inc... E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.