User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 7 /ng/12/20/02
ES46
Description (added 3/3/1997; modified 7/7/1997):
When a DMA controller is in a mode that clears DE (i.e., TM = 0xx), if the
core performs an external access with wait states or there is a transfer
stall (see Appendix B, Section B.3.4.2 in the DSP56300 Family Manual) or
a conditional transfer interlock (see Appendix B, Section B.3.5.1) during
the last DMA channel transfer, there will be one additional DMA word
transfer.
Workaround: There are three general system-dependent workarounds
for this problem. The user should test the system using these
workarounds to determine which one to use in the particular system to
overcome this problem. The workarounds are:
Workaround 1:
a. Prepare one additional memory word in the source and destination
buffers. This data should be ignored.
b. Activate a DMA Interrupt Service Routine (ISR) or poll the DTD bit to
ensure block transfer completeness. In the DMA ISR or the handler
routine after status polling, reload the values of the address registers.
Workaround 2:
a. Use a DMA mode that does not clear DE (i.e., TM = 1xx) and activate
the DMA interrupt.
b. In the ISR, execute the following operations in the order listed: clear
DE, update the address registers, and set DE.
Workaround 3:
a. Use a DMA mode that does not clear DE (i.e., TM = 1xx).
b. Change the address mode from linear addressing to 2D or from 2D to
3D and use an offset register to update the address automatically at
the end of the block.
Note: If the user can not use one of these workarounds, there may be oth-
er possible system-dependent workarounds.
0F13S
Errata
Number
Errata Description
Applies
to Mask