User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 6 /ng/12/20/02
ES45
Description (added 3/3/1998):
When the Host Command Vector Register (HCVR) is written in
Peripheral Component Interconnect (PCI) mode while the Receive Buffer
Lock Enable (RBLE) bit is set in the DSP PCI Control Register (DPCR), the
Host Data Transfer Complete (HDTC) status bit in DSP PCI Status
Register (DPSR) may be set falsely, thus also causing an HDTC interrupt
if that interrupt has been enabled by the Transfer Complete Interrupt
Enable (TCIE) bit in the DPCR.
Workaround:
Use either one of the following alternatives:
• Clear HDTC, if it is set, by writing it with 1 in the Host Command In-
terface Status Register (ISR).
• Clear HDTC, if it is set, by writing it with 1; use software-dependent
information to distinguish between a false and true HDTC setting.
For example, you do either of the following:
- Alter the destination address pointer if the DSP Receive Data Regis-
ter (DRXR) data is being transferred by the DSP core. The pointer
will be changed if the HDTC setting is true.
- Alter the destination address or counter registers of the DMA chan-
nel if the DRXR data is being transferred by the DMA. The registers
will be changed if the HDTC setting is true.
0F13S
Errata
Number
Errata Description
Applies
to Mask