User`s manual
Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata 1996 - 2002 Motorola pg. 5 /ng/12/20/02
ES44
Description (added 3/3/98):
Let’s say that “channel A” is the DMA channel servicing the HI32, and
that “channel B” is another DMA channel that has been disabled by
software. Then, depending on the DMA Request Source field (DRS[4:0])
of the two channels, channel A may be stalled by channel B being
disabled. Channel A may be stalled when the DMA Channel Enable (DE)
bit in the DMA Control Register is cleared by software in the following
cases:
• DE bit of channel B cleared by software because of
- a Transfer Done from DMA channel 0 (DRSb = 00100) or
- an ESSI1 Receive Data (DRSb = 01100) or
- an FCOP Data Output Buffer Full (DRSb = 10100)
then channel A may be stalled by a Host Slave Receive Data
(DRSa = 11100).
• DE bit of channel B cleared by software because of
- a Transfer Done from DMA channel 1 (DRSb = 00101) or
- an ESSI1 Transmit Data (DRSb = 01101) or
- a VCOP Input Data (DRSb = 10101)
then channel A may be stalled by a Host Master Receive Data
(DRSa = 11101).
• DE bit of channel B cleared by software because of
- a Transfer Done from DMA channel 2 (DRSb = 00110) or
- an SCI Receive Data (DRSb = 01110) or
- a VCOP Output Buffer Full (DRSb = 10110)
then channel A may be stalled by a Host Slave Transmit Data
(DRSa = 11110).
• DE bit of channel B cleared by software because of
- a Transfer Done from DMA channel 3 (DRSb = 00111) or
- an SCI Transmit Data (DRSb = 01111) or
- a VCOP Output Data (DRSb = 10111)
then channel A may be stalled by a Host Master Transmit Data
(DRSa = 11111).
Workaround: Use either one of the following alternatives:
• Clear and set the DE bit of channel A immediately after you clear the
DE bit of channel B.
0F13S
Errata
Number
Errata Description
Applies
to Mask