User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 46 /ng/12/20/02
ED46
Description (added 12/10/2001):
The following sequence gives erroneous results:
1) A different slave on the bus terminates a transaction (for example,
assertion of "stop" ).
2) Immediately afterwards (no more than one PCI clock), the chip’s
memory space control/status register at PCI address ADDR is read
in a single-word transaction. In this transaction, the chip drives to
the bus the data corresponding to the register at PCI address
ADDR+4, instead of the requested ADDR.
NOTE: ADDR is the PCI address of one of the following registers:
HCTR (ADDR=$10) , HSTR (ADDR=$14), or HCVR (ADDR=$18),
and not the data register.
Workaround:
The user should find a way to set/clear at least one bit in the control/status
registers to clearly differentiate between them. For example, you can set
HNMI in the HCVR, as this bit will always be 0 in the HSTR. If NMI
cannot be used, then HCVR{HV4,HV3,HV2} and HSTR{HF5,HF4,HF3}
can be set in any combinations that distinguish between HCVR and HSTR
data reads.
Pertains to:
DSP56301 User’s Manual: Put this errata text as a note in the description
of the HCTR (p.
6-48), the HSTR (p. 6-57), and the HCVR (p. 6-59). These page numbers
are for Revision 3 of the manual.
DSP56305 User’s Manual: Put this errata text as a note in the description
of the HCTR (p. 6-54), the HSTR (p. 6-68), and the HCVR (p. 6-72). These
page numbers are for Revision 1of the manual.
0F13S
ED50
Description (added 9/10/1996 as ES29; reclassified as a
documentation erratum on 8/2/2002):
When the SCI transmitter is used in Synchronous mode, the last bit
of the transmitted byte might be truncated to the half of the serial
cycle.
Workaround: Not available.
0F13S
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