User`s manual
Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata 1996 - 2002 Motorola pg. 4 /ng/12/20/02
ES37
Description (added 9/2/1997):
In PCI mode, improper HI32 operation may result if the HTXR/HRXS
registers are accessed by the PCI master at byte address Base_Address +
(N × 2048 + 16), where N is an integer from 1–31.
Workaround:
Not available.
0F13S
ES41
Description (added 9/15/1997):
The HCLK pin of the HI32 presents an input capacitive load of almost 30
pF, which exceeds the permissible maximum load of 12 pF as specified in
the PCI Specification Version 2.1. This may cause improper HI32
operation in PCI systems.
Note: The effect of this extra load may vary from system to system, de-
pending on PCI clock driver strength.
Workaround:
Use a zero-propagation-delay external PLL device (e.g., CY2305) to
buffer the PCI clock signal. This solution does not enable spread-
spectrum PCI clocking.
0F13S
ES42
Description (added 2/27/1998):
When a Direct Memory Access (DMA) channel is in Line mode (i.e., the
DMA Transfer Mode is DTM = 010) with address modes defined by
DMA Three Dimensional mode D3D = 0 and DMA = 10010x (i.e., the
DMA Counter (DCO) is in mode A), and the DCO value is greater than
$FFF, then the DMA does not function properly. This address mode
implies “no update” at the destination and “no update” or “post
increment by 1” mode at the source.
Workaround:
Use Block Transfer mode (i.e., DTM = 000). For the DCO and DMA
Address Mode (DAM) settings described in this erratum, the Line
Transfer mode of DMA is identical to its Block Transfer mode, so this
combination is redundant. In fact, a block containing only one line is still
a block.
0F13S
Errata
Number
Errata Description
Applies
to Mask