User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 36 /ng/12/20/02
ED31
Description (added 9/12/1997; modified 9/15/1997; identified as a
Documentation errata 2/1/99):
Programming the ESSI to use an internal frame sync (i.e., SCD2 = 1
in CRB) causes the SC2 and SC1 signals to be programmed as
outputs. If however, the corresponding multiplexed pins are
programmed by the Port Control Register (PCR) to be GPIOs, then
the GPIO Port Direction Register (PRR) chooses their direction, but
this causes the ESSI to use an external frame sync if GPIO is selected.
Note: This errata and workaround apply to both ESSI0 and ESSI1.
Workaround:
To assure correct operation, either program the GPIO pins as
outputs or configure the pins in the PCR as ESSI signals.
Note: The default selection for these signals after reset is GPIO.
Pertains to: UM, Section 7.4.2.4, “CRB Serial Control Direction 2
(SCD2) Bit 4”
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ED32
Description (added 11/9/98; identified as a Documentation errata
2/1/99):
When returning from a long interrupt (by RTI instruction), and the
first instruction after the RTI is a move to a DALU register (A, B, X,
Y), the move may not be correct, if the 16-bit arithmetic mode bit (bit
17 of SR) is changed due to the restoring of SR after RTI.
Workaround:
Replace the RTI with the following sequence:
movec ssl,sr
nop
rti
Pertains to: DSP56300 Family Manual. Add a new section to
Appendix B that is entitled “Sixteen-Bit Compatibility Mode
Restrictions.”
0F13S
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