User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 34 /ng/12/20/02
ED26
Description (added 1/6/99):
The specification DMA Chapter is wrong.
“Due to the DSP56300 Core pipeline, after DE bit in DCRx is set, the
corresponding DTDx bit in DSTR will be cleared only after two
instruction cycles.”
Should be replaced with:
“Due to the DSP56300 Core pipeline, after DE bit in DCRx is set, the
corresponding DTDx bit in DSTR will be cleared only after three
instruction cycles.”
0F13S
ED28
Description (added 1/7/1997; identified as Documentation Errata
2/1/99):
When two consecutive LAs have a conditional branch instruction at
LA-1 of the internal loop, the part does not operate properly. For
example, the following sequence may generate incorrect results:
DO #5, LABEL1
NOP
DO #4, LABEL2
NOP
MOVE (R0) +
BSCC _DEST ; conditional branch at LA-1 of
internal loop
NOP ; internal LA
LABEL2
NOP ; external LA
LABEL1
NOP
NOP
_DEST NOP
NOP
RTS
Workaround: Put an additional NOP between LABEL2 and
LABEL1.
Pertains to: DSP56300 Family Manual, Appendix B, Section B-4.1.3,
“At LA-1.”
0F13S
Errata
Number
Document Update
Applies
to Mask