User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 33 /ng/12/20/02
ED24
Description (added 11/24/98):
The technical datasheet supplies a maximum value for internal
supply current in Normal, Wait, and Stop modes. These values will
be removed because we will specify only a "Typical" current.
Workaround:
This is a documentation update.
0F13S
ED25
Description (added 12/16/98):
Current definition:
HDTC is set if SRRQ and MRRQ are cleared (i.e. the host-to-DSP
data path is emptied by DSP56300 core reads) under one of the
following conditions:
• a non-exclusive PCI write transaction to the HTXR termi-
nates or completes
• HLOCK
is negated after the completion of an exclusive write
access to the HTXR
• the HI32 initiates a read transaction. The HI32 disconnects
(retry or disconnect-C) forthcoming write accesses to the
HTXR as long as HDTC is set.
New definition:
HDTC is set if SRRQ and MRRQ are cleared (i.e. the host-to-DSP
data path is emptied by DSP56300 Core reads) under one of the
following conditions:
• a non-exclusive PCI write transaction to the HTXR termi-
nates or completes
• HLOCK
is negated after the completion of an exclusive write
access to the HTXR. The HI32 disconnects (retry or discon-
nect-C) forthcoming write accesses to the HTXR as long as
HDTC is set.
Note: The HDTC bit is not set after a read transaction initiated by
the HI32 as a PCI master.
Workaround:
NTR
0F13S
Errata
Number
Document Update
Applies
to Mask