User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 31 /ng/12/20/02
ED10
Description (added 5/13/98):
The HI32 may operate improperly in PCI mode when the TWSD bit
is set in the HCTR register.
Workaround:
Do not set the TWSD bit in the HCTR register; this bit is reserved.
This is a documentation change.
0F13S
ED12
Description (added 5/13/98):
When the HI32 is in PCI mode, the HTF control bits affect the
address insertion (the IAE bit is set in the DPCR register) in the same
way they affect the transferred data.
Address as appears on the PCI bus: $12345678
HTF[1:0] Inserted Address
00 $005678, $001234
01 $345678
10 $345678
11 $123456
Workaround:
This is a documentation update.
0F13S
ED13
Description (added 5/15/98):
When the HI32 is in PCI mode, the Insert Address Enable control bit
(IAE=1) can be set only with the Receive Buffer Lock Enable control
bit set (RBLE=1 in the DPCR register.)
0F13S
ED15
Description (added 7/21/98):
The DRAM Control Register (DCR) should not be changed while
refresh is enabled. If refresh is enabled only a write operation that
disables refresh is allowed.
Workaround:
First disable refresh by clearing the BREN bit, than change other bits
in the DCR register, and finally enable refresh by setting the BREN
bit.
0F13S
Errata
Number
Document Update
Applies
to Mask