User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 30 /ng/12/20/02
ED5
Description (added 4/6/1998):
A change is required to the DSP56301 Product Specification, Section
10.6, “Filter Co-Processor (FCOP). The bullet on Input DMA
Activation is modified as follows:
Workaround:
Input DMA Activation: The DMA for input transfers can be
activated only after the FCOP is enabled (FEN set) and the core has
initialized the coefficient bank via the FCIR register. Then the DMA
input channel can be enabled in order to start transferring data
whenever there are free locations in the input FIFO, while the FCOP
state machine grabs data words from that FIFO as required. The
FCOP state machine starts computation as soon as both coefficient
and data banks complete the initialization phase (according to
#filter_count value).
A good practice is to program the input data DMA channel for the
transfer of a single word or a line of 2, 3, or 4 words triggered by the
FDIBE bit in the FCSR register (since the input buffer FIFO depth is
4).
0F13S
ED6
Description (Added 4/9/98):
When the HIRQ
pin is used in pulse mode (HIRH=0 in DCTR), the
LT[7:0] value (in CLAT) should not be zero. This is not a bug but a
documentation update.
0F13S
ED7
Description (added 1/27/98):
When activity passes from one DMA channel to another and the
DMA interface accesses external memory (which requires one or
more wait states), the DACT and DCH status bits in the DMA Status
Register (DSTR) may indicate improper activity status for DMA
Channel 0 (DACT = 1 and DCH[2:0] = 000).
Workaround:
None.
Pertains to: DSP56300 Family Manual, Sections 8.1.6.3 and 8.1.6.4
0F13S
Errata
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