User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 28 /ng/12/20/02
ES124
Description (added 9/11/99) (reclassified from documentation to silicon
errata 11/11/99):
When an external PCI master executes a configuration space read from
the HI32 with an odd number of byte lanes enabled (for example, BE3
–
BE0
= 1000), the DSP drives the parity signal (HPAR) with the wrong
value. This is because the BE3 – BE0 signals are ignored (erroneously)
when generating the parity value during configuration space reads.
Workaround: None.
Pertains to: The HI32 (PCI) chapter of the user’s manual, in the section on
PCI Mode (DCTR[HM]=$1). In Revision 2 of the DSP56301 User’s
Manual, this section is 6.5.2 on page 6-14. The information should
accompany the bullet on Memory-Space and configuration transactions
as a target.
NOTE: Was documentation errata, ED39.
0F13S
Errata
Number
Errata Description
Applies
to Mask