User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 26 /ng/12/20/02
ES115
Description (added 4/19/99):
When a DMA channel (called channel A) is disabled by software clearing
the channel’s DCR[DE] bit, the DTD bit may not get set, and the DMA
end of the block interrupt may not happen if one of the following occurs:
1. There is another channel (channel B) executing EXTERNAL accesses,
and the DE bit of channel A is being cleared by software at the end of the
channel B word transfer - if channel B is in Word transfer mode, or at the
end of the channel B line transfer - if channel B is in Line Transfer mode,
or at the end of the channel B block transfer - if channel B is in Block
transfer mode.
2. This channel (A) is executing EXTERNAL accesses, and the DE bit of
this channel (A) is being cleared by software at the end of the channel B
word transfer - if channel B is in Word transfer mode, or at the end of the
channel B line transfer - if channel B is in Line transfer mode.
Workaround:
Avoid executing a DMA external access when any DMA channel should
be disabled. This can be done as follows. Every time the DMA channel
needs to be disabled by software, the following sequence must be used:
;; initialize an unused DMA channel "C"
movep #DSR_swflag, x:M_DSRC ;; here DSR_swflag is an
;; unused X, Y or P memory
;; location, should
;; be initialized to
;; $800000
;; M_DSRC - address of the
;; channel C DSR register.
0F13S
Errata
Number
Errata Description
Applies
to Mask