User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 25 /ng/12/20/02
ES107
Description (added 12/8/98):
The HDTC status bit (relevant only if the RBLE control bit is set) may not
be set properly when both of the following conditions apply:
a) DSP software clears the HDTC bit while the PCI bus is parked on the
HI32.
b) The PCI master read transaction is initiated by the HI32 while the bus
is still parked on the HI32.
Workaround:
Use one of the following alternatives:
1. Avoid bus parking on the HI32.
2. Enter the Personal Software Reset (HM[2:0]=0) in HDTC ISR.
3. Poll the MRRQ and SRRQ status bits before the start of each master
read transaction (e.g. in MARQ ISR). Start this transaction only when
both MRRQ and SRRQ are cleared. The HDTC status bit should be
cleared by the DSP software as defined in the specification.
0F13S
ES114
Description (added 4/19/99, revised 4/30/99):
A DMA channel may operate improperly when the address mode of this
channel is defined as three-dimensional (D3D=1) and DAM[5:0] = 1xx 1
10 or DAM[5:0] = 01xx 10 (i.e., triple counter mode is E).
Workaround:
Use the triple counter modes C(DAM[1:0]=00) or D(DAM[1:0]=01)
instead of the E(DAM[1:0]=10) mode.
0F13S
Errata
Number
Errata Description
Applies
to Mask