User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 24 /ng/12/20/02
ES104
Description (added 11/20/98):
An improper operation may occur when a DMA channel uses the
following transfer modes:
• DTM(2:0) = 100
• DTM(2:0) = 101
where the DE bit is not automatically cleared at the end of block and the
DMA channel is disabled by software (DE bit is cleared) while it is
triggered for a new transfer.
Workaround:
The DMA channel should be disabled only when it cannot be triggered
by a new transfer. Use one of the following alternatives:
1. The system configuration must guarantee that no DMA trigger can
occur while the DE bit is cleared.
2.The following sequence disables the DMA channel:
a/ Wait until the DTD bit is cleared
b/ Clear the DE bit
c/ Wait until the DTD bit is set
0F13S
Errata
Number
Errata Description
Applies
to Mask