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Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata 1996 - 2002 Motorola pg. 23 /ng/12/20/02
ES102
Description (added 11/9/98):
In regular operation, the VCOP—when enabled in either Equalization,
Decoding or Encoding modes—sets the DREQ flag (Data Request status
bit) in order to ask for data via an interrupt (if enabled) or a DMA
request. This status bit is set at the start of the operation. Each time the
VCOP receives the necessary data and starts the butterfly calculation, it
requests data for the next butterfly calculation session. Whenever either
the DMA or the Core delays its data transfer to the VCOP and theVCOP
has finished calculating all the butterflies for the current stage, the VCOP
stops all its state machine clocks until all data required for the next stage
is entered. Then the VCOP resumes all its clocks and continues to
calculate the next stage.
A problem may occur during the interval when the VCOP finishes
processing the data for the current stage and stops its state machine
clocks to wait for input data for the next stage. Immediately after the next
1, 3, or 5 cycles, the DMA inputs all the necessary data to the VDR
(Viterbi Data Input Register) and the VCOP resumes its clocks. There
may be problems with the decoded bits because of a contention between
the ending stage pipe and the starting stage pipe in the viterbi state
machine pipeline.
Workarounds:
1. Prevent clock stops in the VCOP by increasing either the Viterbi Data
Input interrupt priority or the DMA request priority in the DSP. The
external Core/DMA priority should correspond. For DMA, calculate the
maximum transfer cycles of the rest of the channels to prevent possible
clock stopping (in the VCOP, for 16 states trellis, it takes 32 cycles for 1
stage calculation).
2. Force VCOP clock stopping . Using the Timer, the user can force the
VCOP to wait more than 7 cycles till the VCOP state machine pipeline
stops and then to issue a DMA request (should be evaluated).
0F13S
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