User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 2 /ng/12/20/02
ES28
Description (added 9/10/1996):
If the chip is in Debug mode and the TRST pin is asserted, the chip status
will show the chip status as “User” mode instead of the expected
“Debug” mode, when the status is read afterwards through the JTAG
port.
Workaround: Execute the following JTAG commands before reading the
JTAG status:
a) Enable OnCE
b) DEBUG request
Afterwards, the status bits will reflect the actual status of the chip, and
the DE
pin will acknowledge “re-entering” the Debug mode.
0F13S
ES30
Description (added 11/18/1996):
After the BB
pin output is driven high and released, the pin output
voltage level may not reach V
CC
. The issue depends on the application
board layout and the parameters of the chip process.
Workaround: Use a restricted board layout that includes a 1 kΩ pull-up
resistor connected to the BB
pin with a 100 Ω resistor connected in series
with, and as close as possible to, the pin. The board route from the BB pin
to any component should guarantee the following parameters:
a. Route inductance < 40 nH
b. Route capacitance < 15 pF
c. Input capacitance < 8 pF
Such restrictions guarantee that when BB is driven high (deasserted), the
output voltage level will be above 2.25 V at V
CC
= 3.3 V.
0F13S
Errata
Number
Errata Description
Applies
to Mask