User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 19 /ng/12/20/02
ES85
Description (added 5/3/98):
If both the DMA channel and the core simultaneously access the same
1/4K page of internal memory (X, Y, or program), an improper DMA
channel operation may occur.
Workaround:
Avoid simultaneous DMA and core accesses to the same 1/4K page of
internal memory.
0F13S
ES86
Description (added 4/23/98):
If the HI32 performs a write transaction as a PCI master and the
transaction is disconnected by the target, the value of the MTRQ status
bit in the DPSR register may be wrong.
Workaround:
Do not use an MTRQ status bit-related interrupt or polling. (The related
DMA functionality is not affected by this issue.)
0F13S
ES87
Description (added 5/28/98):
When the HI32 is an active PCI target, it does not set the DPE bit in the
CSTR register if an address parity error occurs.
Workaround :
The Host can get information about the Address Parity status either by
reading the SSE bit (in the CSTR) or by indirectly reading the (e.g. via
Host Command) the APER bit in the DPSR register.
0F13S
Errata
Number
Errata Description
Applies
to Mask