User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 18 /ng/12/20/02
ES84
Description (added 5/13/98):
When software disables a DMA channel (by clearing the DE bit of the
DCR) , the DTD status bit of the channel may not be set if any of the
following events occur:
a. Software disables the DMA channel just before a conditional transfer
stall (Described by App B-3.5.1,UM).
b. Software disables the DMA channel at the end of the block transfer
(that is after the counter is loaded with its initial value and transfer of
the last word of the block is completed).
As a result, the Transfer Done interrupt might not be generated.
Workaround:
Avoid using the instruction sequence causing the conditional transfer
stall (See DSP56300 UM, App B-3.5.1 for description) in fast interrupt
service routines. Every time the DMA channel needs to be disabled by
software, the following sequence must be used :
bclr #DIE,x:M_DCR ; not needed if DIE is cleared
bclr #DE,x:M_DCR
; instead of two instructions above, one ’movep’ instruction ;
may be used
; to clear DIE and DE bits
movep #DCR_Dummy_Value,x:M_DCR
bclr #DE,x:M_DCR
nop
nop
Here, the DCR_Dummy_value is any value of the DCR register that complies
with the following requirements:
•DE is set;
• DIE is set if Transfer Done interrupt request should be generated
and cleared otherwise;
• DRS[4:0] bits must encode a reserved DMA request source (see
the following list of reserved DRS values);
List of reserved DRS[4:0] values (per device):
• DSP56302, DSP56309, DSP56303, DSP56306, DSP56362 —
10101-11111
• DSP56305 — 11011
• DSP56301 — 10011-11011
• DSP56307 — 10111-11111
0F13S
Errata
Number
Errata Description
Applies
to Mask