User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 14 /ng/12/20/02
ES52
Description (added 7/7/1997):
If a memory write transaction to HTXR is retried by the HI32 in Insert
Address mode (i.e., IAE in DPCR is set), the PCI transaction address is
written to the HTXR even if the HTXR is locked after the previous
transaction (i.e., Receive Buffer Lock mode—RBLE in DPCR is set).
Workaround:
Use one of the following alternatives:
a. Typically, the Insert Address mode is used to tell the DSP software
what to do with the transferred PCI data, according to the address
used. Instead, use the Host Commands. The PCI master should send
to the HI32 the Host Command with the Host Vector that indicates
what to do with the PCI data, followed by the data itself.
b. If Insert Address mode must be used, in addition to selecting the
Insert Address mode (by setting IAE in the DPCR) and the Receive
Buffer Lock mode (by setting RBLE in the DPCR), use the PCI
interrupts (HINTA pin of the HI32). When the PCI address and data
are transferred to HTXR, it is locked. Subsequent data should be
transferred to the HTXR only when a PCI interrupt (INTA) is
generated by the HI32. The DSP should generate the PCI interrupt (by
setting HINT in the DCTR) after the HDTC bit in the DPSR is set (i.e.,
the DRXR FIFO is cleared) and the corresponding HDTC interrupt is
generated, if enabled. The PCI master should first clear the INTA
interrupt line (e.g., requesting this via Host Command) and then send
the next data (and address) to the HTXR.
c. This is similar to workaround a, except replace the PCI interrupt with
the Host Flags (HF[5:3] in the DCTR).
0F13S
Errata
Number
Errata Description
Applies
to Mask