User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata  1996 - 2002 Motorola pg. 12 /ng/12/20/02
ES49
Description (added 4/7/1997):
If the HI32 is a PCI master and receives a target disconnect (TDIS = 1 in
DPSR) while the Remaining Data Count (RDC[5:0] in DPSR) value is
zero, the Remaining Data Count Qualifier bit (RDCQ in DPSR) may be
incorrect (i.e., one instead of zero). This happens when a target initiates
the Disconnect Without Data Termination at the last data phase to be
transferred. In this case, the Master Data Transferred bit (MDT in DPSR)
is cleared, correctly indicating that all data is not transferred, but the new
burst length (BL[5:0] in DPMC) and the new address may be calculated
erroneously:
BL[5:0]new = RDC[5:0] + RDCQ = RDCQ,
AR[31:0]new = AR[31:0]old + BL[5:0]old - BL[5:0]new =
AR[31:0]old + BL[5:0]old - RDCQ.
Workaround:
Use one of the following alternatives:
a. If MDT = 0 upon completion of a master transaction (read or write)
while
RDC[5:0] = 0 and RDCQ = 1 and TDIS = 1, reset the HI32 FIFOs (enter
Mode 0) and re-transfer the last word of the disconnected transaction.
b. If MDT = 0 upon completion of a master write transaction while
RDC[5:0] = 0 and RDCQ = 1 and TDIS = 1, clear the DTXM-HRXS
FIFO by setting the DPCR(CLRT) bit and re-transfer the last word of
the disconnected transaction.
c. If MDT = 0 upon completion of a master read transaction while
RDC[5:0] = 0 and RDCQ = 1 and TDIS = 1, the exact amount of
transferred data may be identified by counting the number of data
words received through DRXR register (e.g., using the DMA counter
if the DMA was used to handle master data reads).
0F13S
Errata
Number
Errata Description
Applies
to Mask