User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata 1996 - 2002 Motorola pg. 11 /ng/12/20/02
ES48
Cont.
(Errata #46 continued)
For systems using the HI32 and DMA interface, in which the host
processor stores the exact number (N) of words to receive or transmit, the
following three examples indicate how the workarounds are used:
Transfers from the HI32 to the DSP; DMA reads from DRXR:
a. The host processor writes N words to HTXR with the DMA channel
working in mode 5 (TM = 101) and programmed to receive N words
(DCO initial value equals N 1) with the DMA interrupt enabled.
b. After the DMA has read the N words, it enters the ISR, which disables
the DMA, updates the pointers, and re-enables the DMA.
Note: This is based on Workaround #1 above.
Transfers from the DSP to the HI32; DMA writes to DTXS:
a. The host processor is required to read N words with the DMA chan-
nel working in mode 5 (TM =101) and programmed to transmit N + 6
words (DCO initial value equals N + 5) with the DMA interrupt en-
abled.
b. By the time the host processors completes reading of the N words
from HRXS, the DMA has filled the FIFO and entered the DMA
interrupt. The DMA ISR should disable the DMA, update the
pointers, and generate a software reset to the HI32 by writing 000 to
HM in the DCTR. After this is complete (i.e., HACT in DSR is cleared),
the ISR can re-enable the HI32 and the DMA controller.
Transfers from the DSP to the HI32; DMA writes to DTXM:
a. The host processor is required to read N words with the DMA chan-
nel working in mode 5 (TM =101) and programmed to transmit N + 8
words (DCO initial value equals N +7) with the DMA interrupt en-
abled.
b. By the time the host processors completes reading of the N words
from HRXS, the DMA has filled the FIFO and entered the DMA
interrupt. The DMA ISR should disable the DMA, update the
pointers, and generate a software reset to the HI32 by writing 000 to
HM in the DCTR. After this is complete (i.e., HACT in DSR is cleared),
the ISR can re-enable the HI32 and the DMA controller.
Note: This is the same as a DMA write to DTXS, except for the number
of words for which the DMA is programmed.
0F13S
Errata
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Errata Description
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to Mask