User`s manual

Chip Errata
DSP56305 Digital Signal Processor
Mask: 0F13S
DSP56305 Errata 1996 - 2002 Motorola pg. 10 /ng/12/20/02
ES48
Description (added 4/7/1997; modified 7/7/1997):
Note: This is a subset of Errata #46 (i.e., in every case that errata # 48 oc-
curs, errata #46 occurs, but not vice versa).
When a DMA controller is in a mode that clears DE (i.e., TM = 0xx), and
it transfers data to an external memory with two or more wait states, and
the DSP core performs an external access with wait states or there is a
transfer stall (see Appendix B, Section B.3.4.2 in the DSP56300 Family
Manual) or a conditional transfer interlock (see Appendix B, Section
B.3.5.1) during the last DMA channel transfer, the destination pointer for
a subsequent DMA transfer may not be reprogrammed correctly. There
are two defined workarounds to prevent the occurrence of this condition
and one recovery code that should be used if the workarounds can not be
used in a specific system:
Workaround 1:
a. Use a DMA mode that does not clear DE (i.e., TM = 1xx) and activate
the DMA interrupt.
b. In the DMA ISR, clear DE, update the address registers, and set DE.
Workaround 2:
a. Use a DMA mode that does not clear DE (i.e., TM = 1xx).
b. Change the address mode from linear addressing to 2D or 2D to 3D
and use an offset register to update the address automatically at the
end of the block.
Recovery (to recover if the condition occurs):
a. Enable the DMA interrupt.
b. Use the following code in the DMA ISR:
movep #dummy_source, x:M_DSRi
movep #dummy_dest, x:M_DDRi
movep #0, x:M_DEOi
movep #9E0240, x:M_DCRi ; initiate one
; dummy transfer
; if the bug
occurred, the
; transfer will be to
the
;
old_block_last_dest + 1
; and not to the
dummy_dest
nop
0F13S
Errata
Number
Errata Description
Applies
to Mask