Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S General remark: In order to prevent the use of instructions or sequences of instructions that do not operate correctly, we encourage you to use the “lint563” program to identify such cases and use alternative sequences of instructions.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 9/10/1996): 0F13S If the chip is in Debug mode and the TRST pin is asserted, the chip status will show the chip status as “User” mode instead of the expected “Debug” mode, when the status is read afterwards through the JTAG port.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 2/12/1997): ES32 0F13S Under the PCI specification, a PCI arbiter can park the PCI bus on a specific device by asserting the GNT signal for that device, allowing the device to have virtually instantaneous bus access (i.e, if GNT is asserted for the device, no REQ assertion is required to start a transaction).
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 9/2/1997): ES37 0F13S In PCI mode, improper HI32 operation may result if the HTXR/HRXS registers are accessed by the PCI master at byte address Base_Address + (N × 2048 + 16), where N is an integer from 1–31. Workaround: Not available.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Errata Description Description (added 3/3/98): Let’s say that “channel A” is the DMA channel servicing the HI32, and that “channel B” is another DMA channel that has been disabled by software. Then, depending on the DMA Request Source field (DRS[4:0]) of the two channels, channel A may be stalled by channel B being disabled.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 3/3/1998): 0F13S When the Host Command Vector Register (HCVR) is written in Peripheral Component Interconnect (PCI) mode while the Receive Buffer Lock Enable (RBLE) bit is set in the DSP PCI Control Register (DPCR), the Host Data Transfer Complete (HDTC) status bit in DSP PCI Status Register (DPSR) may be set falsely, thus also causing an HDTC interrupt if that interrupt has bee
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 3/3/1997; modified 7/7/1997): 0F13S When a DMA controller is in a mode that clears DE (i.e., TM = 0xx), if the core performs an external access with wait states or there is a transfer stall (see Appendix B, Section B.3.4.2 in the DSP56300 Family Manual) or a conditional transfer interlock (see Appendix B, Section B.3.5.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description (Errata #46 continued) 0F13S For systems using the HI32 and DMA interface, in which the host processor stores the exact number (N) of words to receive or transmit, the following workarounds can be used: Transfers from the HI32 to the DSP; DMA reads from DRXR: a.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 3/3/1997): 0F13S If the DMA channel and the core access the same 1/4 K internal X data, Y data, or program memory page, and the DMA interrupt is enabled, a false interrupt may occur in addition to the correct one. ES47 Workaround: Ensure that the channel’s DTD status bit in the DSTR is set before jumping to the Interrupt Service Routine (i.e.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 4/7/1997; modified 7/7/1997): 0F13S Note: This is a subset of Errata #46 (i.e., in every case that errata # 48 occurs, errata #46 occurs, but not vice versa). When a DMA controller is in a mode that clears DE (i.e.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description (Errata #46 continued) 0F13S For systems using the HI32 and DMA interface, in which the host processor stores the exact number (N) of words to receive or transmit, the following three examples indicate how the workarounds are used: Transfers from the HI32 to the DSP; DMA reads from DRXR: a.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 4/7/1997): 0F13S If the HI32 is a PCI master and receives a target disconnect (TDIS = 1 in DPSR) while the Remaining Data Count (RDC[5:0] in DPSR) value is zero, the Remaining Data Count Qualifier bit (RDCQ in DPSR) may be incorrect (i.e., one instead of zero). This happens when a target initiates the Disconnect Without Data Termination at the last data phase to be transferred.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 6/9/1997): 0F13S If the HI32 is programmed to operate in Universal Bus mode, a spike may be generated on the HTA pin before it is tri-stated. The spike polarity depends on the HTA pin mode; the spike is positive if the pin is programmed as active low and negative if the pin is programmed to be active high.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 7/7/1997): 0F13S If a memory write transaction to HTXR is retried by the HI32 in Insert Address mode (i.e., IAE in DPCR is set), the PCI transaction address is written to the HTXR even if the HTXR is locked after the previous transaction (i.e., Receive Buffer Lock mode—RBLE in DPCR is set). Workaround: Use one of the following alternatives: a.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 9/25/1997): 0F13S Using the JTAG instruction code 1111 ($F) or 1101 ($D) for the BYPASS instruction may cause the chip to enter Debug mode (which then correctly sets the Status bits (OS[1:0]) in the OnCE Status and Control Register (OSCR[7:6]) and asserts the DE output to acknowledge the Debug mode status). Workaround: Use one of the following alternatives: ES53 a.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 9/10/1996): 0F13S When an instruction is executed in which a data value is written into one of the data registers (i.e., X0, X1, Y0 or Y1), and the immediate next instruction is MOVEP from that data register to an internal Y-I/O register, the data written to the Y-I/O register will be incorrect.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 5/13/98): 0F13S The BL pin may operate improperly when two consecutive manipulation instructions (bset/bclr/bchg) use external memory as the destination.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 5/13/98): 0F13S When software disables a DMA channel (by clearing the DE bit of the DCR) , the DTD status bit of the channel may not be set if any of the following events occur: a. Software disables the DMA channel just before a conditional transfer stall (Described by App B-3.5.1,UM). b.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 5/3/98): ES85 0F13S If both the DMA channel and the core simultaneously access the same 1/4K page of internal memory (X, Y, or program), an improper DMA channel operation may occur. Workaround: Avoid simultaneous DMA and core accesses to the same 1/4K page of internal memory.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 6/25/98): ES89 0F13S If the SCI Receiver is programmed to work with a different serial clock than the SCI Transmitter so that either the Receiver or Transmitter is using the external serial clock and the other is using the internallygenerated serial clock—RCM and TCM in the SCCR are programmed differently)—then the internal serial clock generator will not operate and the SCI po
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 6/25/98)/Modified 4/19/99: 0F13S A deadlock occurs during DMA transfers if all the following conditions exist: 1. DMA transfers data between internal memory and external memory through port A. 2. DMA and the core access the same internal 0.25K memory module. 3. One of the following occurs: a. The bus arbitration system is active, i.e., BG is changing, not tied to ground.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 8/15/98): ES95 0F13S If more than a single DMA channel is enabled while the DSP stays in the WAIT processing state, and triggering one of the DMA channels causes an exit from the WAIT state (See A-6.115, UM), triggering another DMA channel might cause improper DMA operation. Workaround: Assure that only a single DMA channel can be triggered during DSP WAIT state.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 11/9/98): 0F13S In regular operation, the VCOP—when enabled in either Equalization, Decoding or Encoding modes—sets the DREQ flag (Data Request status bit) in order to ask for data via an interrupt (if enabled) or a DMA request. This status bit is set at the start of the operation.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 11/20/98): 0F13S An improper operation may occur when a DMA channel uses the following transfer modes: • DTM(2:0) = 100 • DTM(2:0) = 101 where the DE bit is not automatically cleared at the end of block and the DMA channel is disabled by software (DE bit is cleared) while it is triggered for a new transfer.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 12/8/98): 0F13S The HDTC status bit (relevant only if the RBLE control bit is set) may not be set properly when both of the following conditions apply: a) DSP software clears the HDTC bit while the PCI bus is parked on the HI32. b) The PCI master read transaction is initiated by the HI32 while the bus is still parked on the HI32.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 4/19/99): 0F13S When a DMA channel (called channel A) is disabled by software clearing the channel’s DCR[DE] bit, the DTD bit may not get set, and the DMA end of the block interrupt may not happen if one of the following occurs: 1.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description ;; ;; ;; ;; ;; ;; movep X, Y or P memory location, should be initialized to $000000 M_DDRC address of the channel C DDR register . #TR_LENGTH, x:M_DCOC register .movep ES115 cont. ;; see below the definition ;; of the TR_LENGTH value, ;; M_DCOC - address ;; of the channel C DCO #1f0240, x:M_DCRC ;; M_DCRB - address of the ;; channel C DCR register.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Errata Description Description (added 9/11/99) (reclassified from documentation to silicon errata 11/11/99): 0F13S When an external PCI master executes a configuration space read from the HI32 with an odd number of byte lanes enabled (for example, BE3 – BE0 = 1000), the DSP drives the parity signal (HPAR) with the wrong value.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Documentation Errata Errata Number Applies to Mask Document Update Description: 0F13S XY Memory Data Move does not work properly if X-memory move destination is internal I/O and Y-memory move source is a register used as destination in the previous or next adjacent move from non Y-memory. ED1 This is not a bug, but a documentation update. Any of the following alternatives can be used: a.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 4/6/1998): 0F13S A change is required to the DSP56301 Product Specification, Section 10.6, “Filter Co-Processor (FCOP). The bullet on Input DMA Activation is modified as follows: Workaround: ED5 Input DMA Activation: The DMA for input transfers can be activated only after the FCOP is enabled (FEN set) and the core has initialized the coefficient bank via the FCIR register.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 5/13/98): ED10 0F13S The HI32 may operate improperly in PCI mode when the TWSD bit is set in the HCTR register. Workaround: Do not set the TWSD bit in the HCTR register; this bit is reserved. This is a documentation change.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 9/28/98): ED17 0F13S In all DSP563xx technical datasheets, a note is to be added under "AC Electrical Characteristics" that although the minimum value for "Frequency of Extal" is 0MHz, the device AC test conditions are 15MHz and rated speed.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 11/24/98): ED24 0F13S The technical datasheet supplies a maximum value for internal supply current in Normal, Wait, and Stop modes. These values will be removed because we will specify only a "Typical" current. Workaround: This is a documentation update. Description (added 12/16/98): 0F13S Current definition: HDTC is set if SRRQ and MRRQ are cleared (i.e.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 1/6/99): 0F13S The specification DMA Chapter is wrong. ED26 “Due to the DSP56300 Core pipeline, after DE bit in DCRx is set, the corresponding DTDx bit in DSTR will be cleared only after two instruction cycles.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 9/12/1997; identified as a Documentation errata 2/1/99): ED29 0F13S When the ESSI transmits data with the CRA Word Length Control bits (WL[2:0]) = 100, the ESSI is designed to duplicate the last bit of the 24-bit transmission eight times to fill the 32-bit shifter. Instead, after shifting the 24-bit word correctly, eight 0s are being shifted. Workaround: None at this time.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 9/12/1997; modified 9/15/1997; identified as a Documentation errata 2/1/99): 0F13S Programming the ESSI to use an internal frame sync (i.e., SCD2 = 1 in CRB) causes the SC2 and SC1 signals to be programmed as outputs.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 12/16/98; identified as a Documentation errata 2/1/99): 0F13S When Stack Extension mode is enabled, a use of the instructions BRKcc or ENDDO inside do loops might cause an improper operation. If the loop is non nested and has no nested loop inside it, the erratais relevant only if LA or LC values are being used outside the loop.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update nop_before_label2 nop label2 ..... ..... label1 .... .... 0F13S ; This instruction must be NOP. fix_brk_routine move #1,lc jmp nop_before_label2 ENDDO -----Original code: do #M,label1 ..... ..... do #N,label2 ..... ..... ENDDO ..... ..... ED33 cont. label2 ..... ..... label1 Will be replaced by: do #M, label1 ..... ..... do #N, label2 ..... .....
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Document Update Applies to Mask 0F13S nop_after_jmp NOP ; This instruction must be NOP. ..... ..... label2 ..... ..... label1 .... .... fix_enddo_routine move #1,lc move #nop_after_jmp,la jmp nop_after_jmp ED33 cont. 2) DO FOREVER loops =================== BRKcc ----Original code: do #M,label1 ..... ..... do forever,label2 ..... ..... BRKcc ..... ..... label2 ..... ..... label1 DSP56305 Errata 1996 - 2002 Motorola pg.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Will be replaced by: 0F13S do #M,label1 ..... ..... do forever,label2 ..... ..... JScc fix_brk_forever_routine note: JScc and not Jcc ..... ..... ED33 cont. nop_before_label2 nop label2 ..... ..... label1 .... .... ; <--- ; This instruction must be NOP. fix_brk_forever_routine move ssh,x:<..> ; <..
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update 0F13S do forever,label2 ..... ..... ENDDO ..... ..... label2 ..... ..... label1 Will be replaced by: ED33 cont. do #M,label1 ..... ..... do forever,label2 ..... ..... JSR fix_enddo_routine ; <--- note: JSR and not JMP nop_after_jmp NOP ; This instruction should be NOP ..... ..... label2 ..... ..... label1 .... ....
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 1/5/99; identified as a Documentation errata 2/1/99): 0F13S When stack extansion is enabled, the read result from stack may be improper if two previous executed instructions cause sequential read and write operations with SSH. Two cases are possible: Case 1: For the first executed instruction: move from SSH or bit manipulation on SSH (i.e.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 7/14/99): ED38 0F13S If Port A is used for external accesses, the BAT bits in the AAR3-0 registers must be initialized to the SRAM access type (i.e. BAT = 01) or to the DRAM access type (i.e. BAT = 10). To ensure proper operation of Port A, this initialization must occur even for an AAR register that is not used during any Port A access.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 11/11/99): When an instruction with all the following conditions follows a repeat instruction, then the last move will be corrupted.: 1. The repeated instruction is from external memory. 2. The repeated instruction is a DALU instruction that includes 2 DAL registers, one as a source, and one as destination (e.g. tfr, add). 3.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update 0F13S Description (added on 3/22/2000) ED42 The DMA End-of-Block-Transfer interrupt cannot be used if DMA is operating in the mode in which DE is not cleared at the end of the block transfer (DTM = 100 or 101). Pertains to: DSP56300 Family Manual, Rev. 2, Section 10.4.1.2, “End-of-BlockTransfer Interrupt.” Also, Section 10.5.3.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S Errata Number Applies to Mask Document Update Description (added 12/10/2001): 0F13S The following sequence gives erroneous results: 1) A different slave on the bus terminates a transaction (for example, assertion of "stop" ). 2) Immediately afterwards (no more than one PCI clock), the chip’s memory space control/status register at PCI address ADDR is read in a single-word transaction.
Chip Errata DSP56305 Digital Signal Processor Mask: 0F13S NOTES 1. An over-bar (i.e., xxxx) indicates an active-low signal. 2. The letters in the right column tell which DSP56305 mask numbers apply. 3. The Motorola DSP website has additional documentation updates that can be accessed at the following URL: http://www.motorola-dsp.com/ 4. Information contained in the addendum to the DSP56301 data sheet applies to all members of the DSP56300 core family, as appropriate (i.
