User`s manual

5-8 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Instruction Cache and Memory Features
The Instruction Cache
During non-burst pipeline operation, while an instruction is
executing (i.e., in the instruction latch), the external memory port
may be busy with the following accesses:
1. Fetching an external program word of the next instruction (1
access at most)
2. Data reads/writes for the instruction 3 words back (2
accesses at most)
For example, during the execution of instruction i4, the memory
port is busy with the data transfers of i1, and fetching of i5. In order
to calculate the cycle count of an instruction in the example, we
should add the cycle count of the accesses that are performed
during its execution. An access cycle count is the number of wait
states + 1. The instruction's execution time is in parallel to the access
cycles.
i11 mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0 1do,1di,1po 21 2di 6
i12 macr x0,y0,a 1do,1di,1po 21 2di,1po,3pi 24
i13 nop 1do,1po 18 1do 9
i14 move a,y:(r1)+ 1do,1di,1po 21 2di 6
i15 nop 1pi 3 —
i16 nop 1pi 3 1po,3pi 18
i17 nop 1do 9 1do 9
TOTAL: 257 — 186
i0 nop 1po 9 1po,3pi 15
Example 5-1 Example for i5
1 out-of-page data access 9 cycles
1 in-page data access 3 cycles
1 out-of-page program access 9 cycles
total: 21 cycles
Note: This information is specific for this example (in 2-word or
multi-cycle instructions the behavior may change), and
brought only to explain the cycle count in the table.
Table 5-2 Cycle Count Example With and Without Burst Mode
No Instruction
Burst Mode
Disabled
Burst Mode
Enabled
External
Accesses
Cyc
External
Accesses
Cyc