Stereo System User Manual
Table Of Contents
- Title Page
- Chapter1 Overview
- Chapter2 Signals/Connections
- 2.1 Power
- 2.2 Ground
- 2.3 Clock
- 2.4 PLL
- 2.5 External Memory Expansion Port (Port A)
- 2.6 Interrupt and Mode Control
- 2.7 Host Interface (HI32)
- 2.8 Enhanced Synchronous Serial Interface 0
- 2.9 Enhanced Synchronous Serial Interface 1
- 2.10 Serial Communications Interface (SCI)
- 2.11 Timers
- 2.12 JTAG and OnCE Interface
- Chapter3 Memory Configuration
- Chapter4 Core Configuration
- 4.1 Operating Modes
- 4.2 Bootstrap Program
- 4.3 Central Processor Unit (CPU) Registers
- 4.4 Configuring Interrupts
- 4.5 PLL Control Register (PCTL)
- 4.6 Bus Interface Unit (BIU) Registers
- 4.7 DMA Control Registers 5–0 (DCR[5–0])
- 4.8 Device Identification Register (IDR)
- 4.9 JTAG Identification (ID) Register
- 4.10 JTAG Boundary Scan Register (BSR)
- Chapter5 Programming the Peripherals
- Chapter6 Host Interface (HI32)
- 6.1 Features
- 6.2 Overview
- 6.3 Data Transfer Paths
- 6.4 Reset States
- 6.5 DSP-Side Operating Modes
- 6.6 Host Port Pins
- 6.7 HI32 DSP-Side Programming Model
- 6.7.1 DSP Control Register (DCTR)
- 6.7.2 DSP PCI Control Register (DPCR)
- 6.7.3 DSP PCI Master Control Register (DPMC)
- 6.7.4 DSP PCI Address Register (DPAR)
- 6.7.5 DSP Status Register (DSR)
- 6.7.6 DSP PCI Status Register (DPSR)
- 6.7.7 DSP Receive Data FIFO (DRXR)
- 6.7.8 DSP Master Transmit Data Register (DTXM)
- 6.7.9 DSPSlaveTransmitData Register (DTXS)
- 6.7.10 DSP Host Port GPIO Direction Register (DIRH)
- 6.7.11 DSP Host Port GPIO Data Register (DATH)
- 6.8 Host-Side Programming Model
- 6.8.1 HI32 Control Register (HCTR)
- 6.8.2 Host Interface Status Register (HSTR)
- 6.8.3 Host Command Vector Register (HCVR)
- 6.8.4 Host Master Receive Data Register (HRXM)
- 6.8.5 Host Slave Receive Data Register (HRXS)
- 6.8.6 Host Transmit Data Register (HTXR)
- 6.8.7 Device ID/Vendor ID Configuration Register (CDID/CVID)
- 6.8.8 Status/Command Configuration Register (CSTR/CCMR)
- 6.8.9 Class Code/Revision ID Configuration Register (CCCR/CRID)
- 6.8.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)
- 6.8.11 Memory Space Base Address Configuration Register (CBMA)
- 6.8.12 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)
- 6.8.13 Interrupt Line-Interrupt Pin Configuration Register(CILP)
- 6.9 HI32 Programming Model/Quick Reference
- Chapter7 Enhanced Synchronous Serial Interface (ESSI)
- 7.1 ESSI Enhancements
- 7.2 ESSI Data and Control Signals
- 7.3 Operation
- 7.4 Operating Modes: Normal, Network, and On-Demand
- 7.4.1 Normal/Network/On-Demand Mode Selection
- 7.4.2 Synchronous/Asynchronous Operating Modes
- 7.4.3 Frame Sync Selection
- 7.4.4 Frame Sync Signal Format
- 7.4.5 Frame Sync Length for Multiple Devices
- 7.4.6 Word Length Frame Sync and Data Word Timing
- 7.4.7 Frame Sync Polarity
- 7.4.8 Byte Format (LSB/MSB) for the Transmitter
- 7.4.9 Flags
- 7.5 ESSI Programming Model
- 7.5.1 ESSI Control Register A (CRA)
- 7.5.2 ESSI Control Register B (CRB)
- 7.5.3 ESSI Status Register (SSISR)
- 7.5.4 ESSI Receive Shift Register
- 7.5.5 ESSI Receive Data Register (RX)
- 7.5.6 ESSI Transmit Shift Registers
- 7.5.7 ESSI Transmit Data Registers (TX[2–0])
- 7.5.8 ESSI Time Slot Register (TSR)
- 7.5.9 Transmit Slot Mask Registers (TSMA, TSMB)
- 7.5.10 Receive Slot Mask Registers (RSMA, RSMB)
- 7.6 GPIO Signals and Registers
- Chapter8 Serial Communication Interface (SCI)
- Chapter9 Triple Timer Module
- AppendixA Bootstrap Program
- ChapterB Programming Reference
- Index
Host-Side Programming Model
Host Interface (HI32) 6-49
Table 6-22. Host Interface Control Register (HCTR) Bit Definitions
Bit
Number
Bit Name
Reset
Value
Mode Description
31–20
0 Reserved. Write to zero for future compatibility.
19 TWSD 0 PCI
Target Wait State Disable
Note: Do not set the TWSD bit. This bit is reserved. The HI32 may
operate improperly in PCI mode when the Target Wait State
Disable (TWSD) bit is set.
Disables PCI wait states (which are inserted by deasserting HTRDY
)
during a data phase. If TWSD is cleared and the HI32 is in PCI mode
(DCTR[HM] = $1):
n as the selected target in a read data phase from the HRXS, the
HI32 inserts PCI wait states if the HRXS is empty (HRRQ = 0).
Wait states are inserted until the data is transferred from the DSP
side to the HRXS. Up to eight wait states can be inserted before a
target initiated transaction termination (disconnect-C/Retry) is
generated.
n as the selected target in a write data phase to the HTXR, the HI32
inserts PCI wait states if the HTXR is full (HTRQ = 0). Wait states
are inserted until the data is transferred from the HTXR to the DSP
side. Up to eight wait states can be inserted before a target
initiated transaction termination (disconnect-C/Retry) is generated.
n as the selected target in a write data phase to the HCVR, the HI32
inserts PCI wait states if a host command is pending (HC = 1).
Wait states are inserted until the pending host command is
serviced. Up to eight wait states can be inserted before a target
initiated transaction termination (disconnect-C/Retry) is generated.
If TWSD is set and the HI32 is in the PCI mode (DCTR[HM] = $1):
n as the selected target in a read transaction from the HRXS, the
HI32 generates a target initiated transaction termination
(disconnect-C) if the HRXS is empty (HRRQ = 0).
n as the selected target in a write transaction to the HTXR, the HI32
generates a target initiated transaction termination (disconnect-C)
if the HTXR is full (HTXR = 0).
n as the selected target in a write transaction to the HCVR, the HI32
generates a target initiated transaction termination (disconnect-C)
if a host command is pending (HC = 1).
TWSD is ignored when the HI32 is not in PCI mode (DCTR[HM]≠$1).
The personal hardware reset clears TWSD.
18–17
0
Reserved. Write to zero for future compatibility.
16–14 HS[2–0] 0
UBM
PCI
Host Semaphores
Used by the host processors for software arbitration of mastership over
the HI32. These bits do not affect the HI32 operation and serve only as a
read/write semaphore repository. These bits can be used as a mailbox
between the external hosts. For example, the semaphores can assist
HI32 bus arbitration among several external hosts. All external host
processors that compete for mastership over the HI32 should work
according to the same software protocol for handling over the HI32 from
one host processor to another.