User`s manual

M9328MX1ADS - Rev 2 User’s Manual
32 Support Information MOTOROLA
Support Information
3, 5, 7, 9, 13,
15, 17, 19, 37,
39, 41, 43, 47,
49, 51, 53, 83,
85, 87, 89, 93,
95, 97, 99, 121,
123, 125, 127,
131, 133, 135,
137
D0 — D31 DATA BUS (lines 0—31) — Bidirectional signals for transferring data
between the processor and an external device.
4, 6, 8, 10 ~EB0 — ~EB3 ENABLE BYTE (lines 0—3) —
Active-low outputs that indicate active
data bytes for the current access. ~EB0 corresponds to DATA[31—24],
~EB1 corresponds to DATA[23—16], ~EB2 corresponds to
DATA[15—8], and ~EB3 corresponds to DATA[7—0]
11, 12, 27, 28,
45, 46, 63, 64,
81, 82, 101,
102, 113, 114,
129, 130, 143,
144
VCC VCC (3.0-volts)
14 ~OE OUTPUT ENABLE — Active-low output that indicates that a bus access
is a read access; enables slave devices to drive the data bus.
16 ~WE WRITE ENABLE — Active-low output
18 ~ECB END CURRENT BURST — Active-low input signal asserted by external
burst devices; indicates the end of a burst sequence
20 ~LBA LOAD BURST ADDRESS — Active-low signal asserted during burst
mode accesses; causes the external burst device to load a new starting
burst address
23, 25, 115, 117 DQM0 — DQM3 SDRAM enable bytes (0-3) -
Active-low output signals.
24, 26, 29 —
34, 70, 94, 96,
98, 100, 103 —
105, 116, 118,
122, 124, 126,
128, 132, 134,
136
A{0 — A24
(not in exact
order)
ADDRESS BUS (0-24) - Output lines for addressing external devices.
38 ~BAA BURST ADDRESS ADVANCE — Active-low signal asserted during
burst mode accesses; causes the external burst devices to increment
internal burst counters.
40 ~BCLK BURST CLOCK — Output signal to external burst devices;
synchronizes burst loading and incrementing
42, 44, 77, 79,
106, 110, 112,
138, 141, 142
NC NO CONNECTION
Table 3-1 SODIMM Connector J2 Signal Descriptions (Continued)
Pin Mnemonic Signal