User`s manual

Configuration and Operation

Operation

User’s Manual M9328MX1ADS - Rev 2

MOTOROLA Configuration and Operation 15

Figure 2-5 SDRAM Interface

2.3.3 Memory Map

Table 2-5 represents the memory mapping for the external peripherals on the

M9328MX1ADS board. Note the Sync Flash and the Ethernet Controller have

repeated memory blocks due to the fact they do not take up the entire address

space of the associated chip select. Software can access the same physical

memory location at several different addresses. For instance SDRAM uses the

entire 64 MB address space allowed for CSD0. The Sync Flash occupies only

16 MBs of the 64 MB space available to CSD1, so its memory is repeated 4

times. CS4 covers 16 MB allowing many repetitions of the Ethernet chip’s

internal registers.

RAS

CAS

DQM0

SDWE

MA1..11

D0..15

SDCE

SDCLK

DQM1

RAS

CAS

UDQM

A0..10

D0..15

16MX16-Bit SDRAM

CLK

CKE

LDQM

16MX16-Bit SDRAM

CS2

A11

BA0

BA1

BA0

BA2

BA1

D0..15D16..31

UDQM

LDQMDQM2

DQM3