User`s guide

66 CPU32 Emulation
Chapter 5: Connecting and Configuring the Emulator
Designing a Target System for the Emulator
The following signals should be available at the BDM port:
BDM signal definitions
Mnemonic Name Direction Signal Description
GND Ground
BKPT
Breakpoint Input
(to target)
Signals a hardware breakpoint. Also used to
place the CPU32 in background debug mode.
Active low
DSCLK Development
system clock
Input Serial input clock
FREEZE Freeze Output Indicates BDM mode
QUOT Quotient out Output Quotient bit of the polynomial divider. Not used in
BDM mode.
RESET
Reset Output Indicates system reset
IFETCH
Instruction fetch Output Indicates when the CPU is performing an
instruction word prefetch and when the
instruction pipeline has been flushed (active low)
DSI Development
serial in
Input BDM data input
V
DD
Output Target power (+5 V or +3.3 V)
IPIPE
Instruction pipe Output Used to track the movement of words through the
instruction pipeline (active low)
DSO Development
serial out
Output BDM data output
DS
Data strobe Output During read, indicates ready to receive valid data;
during write
BERR
Bus error Input Used to terminate target memory cycles (optional)