User`s guide

Status bit definition and encodings
This section describes symbol information that has been set up by the
preprocessor interface configuration software and information about the
available inverse assemblers including filtering and debug monitors.
The table below is specifically for a state configuration. The timing
configurations have many of the same signals, and those signals are
represented by the same symbols used for state configurations.
HP E2480A STAT Bit Description
Bit STAT Label Description
0
~ShoCy When this bit is asserted, it indicates the
execution of an internal (show) cycle.
1
Rd/~Wr Indicates the direction of the transfer.
2
~IFtch Indicates the bus cycle is an instruction fetch.
3
~PFlsh Indicates the instruction pipe has been flushed.
4:5
Sizx Indicates the number of bytes being written or
capable of being read.
6:7
DSAckx Indicates the port size (in bytes) of the
peripheral being read from/ written to.
8
~BErr Indicates that the bus cycle terminated with an
error.
9
~Freeze When asserted, indicates the microcontroller is
in background mode.
10
~Bkpt Indicates a hardware breakpoint has been
encountered.
11
~BGAck When asserted, indicates the microcontroller
does not own the bus.
12:14
FCx These bits indicate the area of memory with
which a transfer is taking place.
Analyzing the Target System
Status bit definition and encodings
3–6 E2480A Motorola CPU32 Preprocessor Interface