user manual

Instruction Set
Instruction Set Summary
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA Instruction Set 99
JSR opr
JSR opr
JSR opr ,X
JSR opr ,X
JSR ,X
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
—————
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
5
6
7
6
5
LDA # opr
LDA opr
LDA opr
LDA opr ,X
LDA opr ,X
LDA ,X
Load Accumulator with Memory Byte A ← (M) — — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LDX # opr
LDX opr
LDX opr
LDX opr ,X
LDX opr ,X
LDX ,X
Load Index Register with Memory Byte X ← (M) — — ↕ ↕—
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LSL opr
LSLA
LSLX
LSL opr ,X
LSL ,X
Logical Shift Left (Same as ASL) — — ↕ ↕↕
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
3
6
5
LSR opr
LSRA
LSRX
LSR opr ,X
LSR ,X
Logical Shift Right — — 0 ↕↕
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
ff
5
3
3
6
5
MUL Unsigned Multiply X : A ← (X) × (A) 0 — — — 0 INH 42 11
NEG opr
NEGA
NEGX
NEG opr ,X
NEG ,X
Negate Byte (Two’s Complement)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
—— ↕ ↕↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
dd
ff
5
3
3
6
5
NOP No Operation ————— INH 9D 2
ORA # opr
ORA opr
ORA opr
ORA opr ,X
ORA opr ,X
ORA ,X
Logical OR Accumulator with Memory A ← (A) ∨ (M) — — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ROL opr
ROLA
ROLX
ROL opr ,X
ROL ,X
Rotate Byte Left through Carry Bit — — ↕ ↕↕
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
ff
5
3
3
6
5
Table 10-6. Instruction Set Summary (Continued)
Source
Form
Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
C
b0
b7
0
b0
b7
C0
C
b0
b7