user manual

Instruction Set
General Release Specification MC68HC05RC16 — Rev. 3.0
96 Instruction Set MOTOROLA
10.5 Instruction Set Summary
Table 10-6. Instruction Set Summary
Source
Form
Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
ADC # opr
ADC opr
ADC opr
ADC opr ,X
ADC opr ,X
ADC ,X
Add with Carry A ← (A) + (M) + (C) ↕— ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ADD # opr
ADD opr
ADD opr
ADD opr ,X
ADD opr ,X
ADD ,X
Add without Carry A ← (A) + (M) ↕— ↕ ↕↕
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
AND # opr
AND opr
AN D opr
AND opr ,X
AND opr ,X
AND ,X
Logical AND A ← (A) ∧ (M) — — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ASL opr
ASLA
ASLX
ASL opr ,X
ASL ,X
Arithmetic Shift Left (Same as LSL) — — ↕ ↕↕
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
3
6
5
ASR opr
ASRA
ASRX
ASR opr ,X
ASR ,X
Arithmetic Shift Right — — ↕ ↕↕
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
ff
5
3
3
6
5
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? C = 0 ————— REL 24 rr 3
BCLR n opr Clear Bit n Mn ← 0 —————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? C = 1 ————— REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? Z = 1 ————— REL 27 rr 3
BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 + rel ? H = 0 ————— REL 28 rr 3
BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 + rel ? H = 1 ————— REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? C ∨ Z = 0 ————— REL 22 rr 3
BHS rel Branch if Higher or Same PC ← (PC) + 2 + rel ? C = 0 ————— REL 24 rr 3
C
b0
b7
0
b0
b7
C