user manual

MC68HC05RC16 — Rev. 3.0 General Release Specification MOTOROLA Resets 47
Resets
External Reset (RESET)
Figure 5-2. Reset and POR Timing Diagram
PCH PCL
OSC1
2
RESET
5
INTERNAL
PROCESSOR
INTERNAL
ADDRESS
BUS
1
3FFE 3FFF
V
DD
4064 t
CYC
t
CYC
t
RL
INTERNAL
DATA
BUS
1
3FFE3FFE3FFE 3FFE NEW PC3FFF
NOTES:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
4. V
DD
must fall to a level lower than V
POR
to be recognized as a power-on reset.
5. The
LPRST pin resets the CPU like RESET. However, 4064 POR cycles are executed first, before the reset vector address appears on the
internal address bus. (See 5.4 Low-Power External Reset (LPRST).)
3
NEW NEW OP
CODEPCLPCH
NEW PC NEW PC
OP
CODE
NEW PC
CLOCK
1
0 V
> V
POR
4