Microcontroller User's Manual

MOTOROLA Chapter 2. ColdFire Core 2-9

Additions to the Instruction Set Architecture

2.4 Additions to the Instruction Set Architecture

The original ColdFire instruction set architecture (ISA) was derived from the

M68000-family opcodes based on extensive analysis of embedded application code. After

the initial ColdFire compilers were created, developers identified ISA additions that would

enhance both code density and overall performance. Additionally, as users implemented

ColdFire-based designs into a wide range of embedded systems, they identified frequently

used instruction sequences that could be improved by the creation of new instructions. This

observation was especially prevalent in development environments that made use of

substantial amounts of assembly language code.

Table 2-4 summarizes the new instructions added to Revision A+ ISA. For more details see

Section 2.14, “ColdFire Instruction Set Architecture Enhancements.”

D0-D7 0x(0,1)80-0x(0,1)87 No Data registers 0-7 (0 = load, 1 = store)

A0-A7 0x(0,1)88-0x(0,1)8F No Address registers 0-7 (0 = load, 1 = store)

A7 is user stack pointer

Processor Miscellaneous Registers

OTHER_A7 0x800 No Other stack pointer

VBR 0x801 Yes Vector base register

MACSR 0x804 No MAC status register

MASK 0x805 No MAC address mask register

ACC0-ACC3 0x806, 0x809,

0x80A, 0x80B

No MAC accumulators 0-3

ACCext01 0x807 No MAC accumulator 0, 1 extension bytes

ACCext23 0x808 No MAC accumulator 2, 3 extension bytes

SR 0x80E No Status register

PC 0x80F Yes Program counter

Local Memory Registers

FLASHBAR 0xC04 Yes Flash base address register

RAMBAR 0xC05 Yes SRAM base address register

Table 2-3. ColdFire CPU Registers (continued)

Name CPU Space (Rc)

Written with

MOVEC