Microcontroller User's Manual

viii MCF5282 User’s Manual MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
6.5 Flash Security Operation .................................................................................. 6-23
6.5.1 Back Door Access......................................................................................... 6-24
6.5.2 Erase Verify Check....................................................................................... 6-24
6.6 Reset.................................................................................................................. 6-24
6.7 Interrupts........................................................................................................... 6-25
Chapter 7
Power Management
7.1 Features............................................................................................................... 7-1
7.2 Memory Map and Registers................................................................................ 7-1
7.2.1 Programming Model....................................................................................... 7-1
7.2.2 Memory Map .................................................................................................. 7-2
7.2.3 Register Descriptions...................................................................................... 7-2
7.3 Functional Description........................................................................................ 7-5
7.3.1 Low-Power Modes.......................................................................................... 7-5
7.3.2 Peripheral Behavior in Low-Power Modes .................................................... 7-7
7.3.3 Summary of Peripheral State During Low-Power Modes............................ 7-16
Chapter 8
System Control Module (SCM)
8.1 Overview............................................................................................................. 8-1
8.2 Features............................................................................................................... 8-1
8.3 Memory Map and Register Definition................................................................ 8-2
8.4 Register Descriptions.......................................................................................... 8-3
8.4.1 Internal Peripheral System Base Address Register (IPSBAR)....................... 8-3
8.4.2 Memory Base Address Register (RAMBAR) ................................................ 8-4
8.4.3 Core Reset Status Register (CRSR)................................................................ 8-6
8.4.4 Core Watchdog Control Register (CWCR) .................................................... 8-6
8.4.5 Core Watchdog Service Register (CWSR)..................................................... 8-9
8.5 Internal Bus Arbitration ...................................................................................... 8-9
8.5.1 Overview....................................................................................................... 8-11
8.5.2 Arbitration Algorithms ................................................................................. 8-11
8.5.3 Bus Master Park Register (MPARK)............................................................ 8-12
8.6 System Access Control Unit (SACU)............................................................... 8-14
8.6.1 Overview....................................................................................................... 8-14
8.6.2 Features......................................................................................................... 8-14
8.6.3 Memory Map/Register Definition ................................................................ 8-15