Microcontroller User's Manual

MOTOROLA Appendix A. Register Memory Map A-21
IPSBAR +
0x1C_0010
Rx Global Mask RXGMASK 32
IPSBAR +
0x1C_0014
Rx Buffer 14 Mask RX14MASK 32
IPSBAR +
0x1C_0018
Rx Buffer 15 Mask RX15MASK 32
IPSBAR +
0x1C_0020
Error and Status ESR 16
IPSBAR +
0x1C_0022
Interrupt Masks IMASK 16
IPSBAR +
0x1C_0024
Interrupt Flags IFLAG 16
IPSBAR +
0x1C_0026
Rx Error Counters RXERRCNT 8
IPSBAR +
0x1C_0027
Tx Error Counter TXERRCNT 8
IPSBAR +
0x1C_0080
Message Buffer 0 - Message Buffer 15 MBUFF0–
MBUFF15
16x16bytes
Flash Registers
IPSBAR +
0x1D_0000
CFM Configuration Register CFMMCR 16
IPSBAR +
0x1D_0002
CFM Clock Divider Register CFMCLKD 8
IPSBAR +
0x1D_0008
CFM Security Register
CFMSEC
32
IPSBAR +
0x1D_0010
CFM Protection Register CFMPROT 32
IPSBAR +
0x1D_0014
CFM Supervisor Access Register CFMSACC 32
IPSBAR +
0x1D_0018
CFM Data Access Register CFMDACC 32
IPSBAR +
0x1D_0020
CFM User Status Register CFMUSTAT 8
IPSBAR +
0x1D_0024
CFM Command Register CFMCMD 8
1
The DMA module originally supported a left-justified 16-bit byte count register (BCR). This function was
later reimplemented as a right-justified 24-bit BCR. The operation of the DMA and the interpretation of
the BCR is controlled by the MPARK[BCR24BIT]. See Chapter Chapter 8, “System Control Module
(SCM)” for more details.
2
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software
reset command. That is, if channel operation is not disabled, undesirable results may occur.
Table A-3. Register Memory Map (Continued)
Address Name Mnemonic Size