Microcontroller User's Manual
MOTOROLA Appendix A. Register Memory Map A-11
IPSBAR + 0xD54 Interrupt Control Register 1-20 ICR120 8
IPSBAR + 0xD55 Interrupt Control Register 1-21 ICR121 8
IPSBAR + 0xD56 Interrupt Control Register 1-22 ICR122 8
IPSBAR + 0xD57 Interrupt Control Register 1-23 ICR123 8
IPSBAR + 0xD58 Interrupt Control Register 1-24 ICR124 8
IPSBAR + 0xD59 Interrupt Control Register 1-25 ICR125 8
IPSBAR + 0xD5A Interrupt Control Register 1-26 ICR126 8
IPSBAR + 0xDE0 Software Interrupt Acknowledge Register 1 SWACKR1 8
IPSBAR + 0xDE4 Level 1 Interrupt Acknowledge Register 1 L1IACKR1 8
IPSBAR + 0xDE8 Level 2 Interrupt Acknowledge Register 1 L2IACKR1 8
IPSBAR + 0xDEC Level 3 Interrupt Acknowledge Register 1 L3IACKR1 8
IPSBAR + 0xDF0 Level 4 Interrupt Acknowledge Register 1 L4IACKR1 8
IPSBAR + 0xDF4 Level 5 Interrupt Acknowledge Register 1 L5IACKR1 8
IPSBAR + 0xDF8 Level 6 Interrupt Acknowledge Register 1 L6IACKR1 8
IPSBAR + 0xDFC Level 7 Interrupt Acknowledge Register 1 L7IACKR1 8
Global Interrupt Acknowledge Cycle Registers
IPSBAR + 0xFE0 Global Software Interrupt Acknowledge Register GSWACKR 8
IPSBAR + 0xFE4 Global Level 1 Interrupt Acknowledge Register GL1IACKR 8
IPSBAR + 0xFE8 Global Level 2 Interrupt Acknowledge Register GL2IACKR 8
IPSBAR + 0xFEC Global Level 3 Interrupt Acknowledge Register GL3IACKR 8
IPSBAR + 0xFF0 Global Level 4 Interrupt Acknowledge Register GL4IACKR 8
IPSBAR + 0xFF4 Global Level 5 Interrupt Acknowledge Register GL5IACKR 8
IPSBAR + 0xFF8 Global Level 6 Interrupt Acknowledge Register GL6IACKR 8
IPSBAR + 0xFFC Global Level 7 Interrupt Acknowledge Register GL7IACKR 8
FEC Registers
IPSBAR + 0x1004 Interrupt Event Register EIR 32
IPSBAR + 0x1008 Interrupt Mask Register EIMR 32
IPSBAR + 0x1010 Receive Descriptor Active Register RDAR 32
IPSBAR + 0x1014 Transmit Descriptor Active Register XDAR 32
IPSBAR + 0x1024 Ethernet Control Register ECR 32
IPSBAR + 0x1040 MII Data Register MDATA 32
IPSBAR + 0x1044 MII Speed Control Register MSCR 32
IPSBAR + 0x1064 MIB Control/Status Register MIBC 32
IPSBAR + 0x1084 Receive Control Register RCR 32
IPSBAR + 0x10C4 Transmit Control Register TCR 32
Table A-3. Register Memory Map (Continued)
Address Name Mnemonic Size