Microcontroller User's Manual

MOTOROLA Appendix A. Register Memory Map A-7
IPSBAR + 0x2BC (Read) Reserved
3
8
(Write) UART Output Port Bit Reset Command
Register 2
UIP02 8
I
2
C Registers
IPSBAR + 0x300 I
2
C Address Register I2ADR 8
IPSBAR + 0x304 I
2
C Frequency Divider Register I2FDR 8
IPSBAR + 0x308 I
2
C Control Register I2CR 8
IPSBAR + 0x30C I
2
C Status Register I2SR 8
IPSBAR + 0x310 I
2
C Data I/O Register I2DR 8
QSPI Registers
IPSBAR + 0x340 QSPI Mode Register QMR 16
IPSBAR + 0x344 QSPI Delay Register QDLYR 16
IPSBAR + 0x348 QSPI Wrap Register QWR 16
IPSBAR + 0x34C QSPI Interrupt Register QIR 16
IPSBAR + 0x350 QSPI Address Register QAR 16
IPSBAR + 0x354 QSPI Data Register QDR 16
DMA Timer Registers
IPSBAR + 0x400 DMA Timer Mode Register 0 DTMR0 16
IPSBAR + 0x402 DMA Timer Extended Mode Register 0 DTXMR0 8
IPSBAR + 0x403 DMA Timer Event Register 0 DTER0 8
IPSBAR + 0x404 DMA Timer Reference Register 0 DTRR0 32
IPSBAR + 0x408 DMA Timer Capture Register 0 DTCR0 32
IPSBAR + 0x40C DMA Timer Counter Register 0 DTCN0 32
IPSBAR + 0x440 DMA Timer Mode Register 1 DTMR1 16
IPSBAR + 0x442 DMA Timer Extended Mode Register 1 DTXMR1 8
IPSBAR + 0x443 DMA Timer Event Register 1 DTER1 8
IPSBAR + 0x444 DMA Timer Reference Register 1 DTRR1 32
IPSBAR + 0x448 DMA Timer Capture Register 1 DTCR1 32
IPSBAR + 0x44C DMA Timer Counter Register 1 DTCN1 32
IPSBAR + 0x480 DMA Timer Mode Register 2 DTMR2 16
IPSBAR + 0x482 DMA Timer Extended Mode Register 2 DTXMR2 8
IPSBAR + 0x483 DMA Timer Event Register 2 DTER2 8
IPSBAR + 0x484 DMA Timer Reference Register 2 DTRR2 32
IPSBAR + 0x488 DMA Timer Capture Register 2 DTCR2 32
IPSBAR + 0x48C DMA Timer Counter Register 2 DTCN2 32
Table A-3. Register Memory Map (Continued)
Address Name Mnemonic Size